| /tf-a-ffa_el3_spmc/lib/extensions/sve/ |
| A D | sve.c | 28 void sve_enable(cpu_context_t *context) in sve_enable() argument
36 cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); in sve_enable()
40 write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); in sve_enable()
43 write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, in sve_enable()
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| /tf-a-ffa_el3_spmc/bl31/ |
| A D | bl31_context_mgmt.c | 31 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
35 set_cpu_data(cpu_context[security_state], context); in cm_set_context()
56 void cm_set_context_by_index(unsigned int cpu_idx, void *context, in cm_set_context_by_index() argument
61 set_cpu_data_by_index(cpu_idx, cpu_context[security_state], context); in cm_set_context_by_index()
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| /tf-a-ffa_el3_spmc/include/lib/el3_runtime/ |
| A D | context_mgmt.h | 28 void *context,
31 void cm_set_context(void *context, uint32_t security_state);
62 static inline void cm_set_next_context(void *context) in cm_set_next_context() argument
80 : : "r" (context)); in cm_set_next_context()
85 void cm_set_next_context(void *context);
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| /tf-a-ffa_el3_spmc/drivers/nxp/crypto/caam/src/auth/ |
| A D | hash.c | 64 int hash_update(enum hash_algo algo, void *context, void *data_ptr, in hash_update() argument
67 struct hash_ctx *ctx = context; in hash_update()
111 int hash_final(enum hash_algo algo, void *context, void *hash_ptr, in hash_final() argument
115 struct hash_ctx *ctx = context; in hash_final()
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| /tf-a-ffa_el3_spmc/bl32/sp_min/ |
| A D | sp_min_main.c | 79 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
82 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context; in cm_set_context()
102 void cm_set_context_by_index(unsigned int cpu_idx, void *context, in cm_set_context_by_index() argument
106 sp_min_cpu_ctx_ptr[cpu_idx] = context; in cm_set_context_by_index()
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| /tf-a-ffa_el3_spmc/include/drivers/nxp/crypto/caam/ |
| A D | hash.h | 80 int hash_update(enum hash_algo algo, void *context, void *data_ptr,
82 int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
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| /tf-a-ffa_el3_spmc/docs/security_advisories/ |
| A D | security-advisory-tfv-8.rst | 26 When taking an exception to EL3, BL31 saves the CPU context. The aim is to
29 ``x0`` to ``x3`` are not part of the CPU context saved on the stack.
33 into the CPU context, typically using one of the ``SMC_RETx()`` macros provided
38 CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
39 can be seen in the ``lib/el3_runtime/aarch64/context.S`` file at line 339
46 * CPU context. x30 register must be explicitly restored by the caller.
53 remaining ones are left unchanged in the CPU context. As a result,
67 For this reason, TF-A does not save ``x0`` to ``x3`` in the CPU context on an
90 * spsr, lr, sp registers and the `scr` register to the SMC context on entry
97 /* Save r0 - r12 in the SMC context */
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| A D | security-advisory-tfv-5.rst | 45 sensible default values in the secure context.
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| A D | security-advisory-tfv-7.rst | 79 context, where the risk is deemed low enough. This approach enables mitigation
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| A D | security-advisory-tfv-4.rst | 67 In this context, the AArch32 BL1 image might fail to detect potential integer
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| /tf-a-ffa_el3_spmc/bl1/aarch64/ |
| A D | bl1_context_mgmt.c | 27 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
30 bl1_cpu_context_ptr[security_state] = context; in cm_set_context()
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| /tf-a-ffa_el3_spmc/bl1/aarch32/ |
| A D | bl1_context_mgmt.c | 56 void cm_set_next_context(void *context) in cm_set_next_context() argument
58 assert(context != NULL); in cm_set_next_context()
59 bl1_next_cpu_context_ptr = context; in cm_set_next_context()
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| /tf-a-ffa_el3_spmc/include/lib/extensions/ |
| A D | sve.h | 12 void sve_enable(cpu_context_t *context);
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| /tf-a-ffa_el3_spmc/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 37 context.
44 to programming. See `PSCI CPU context management`_ for more
45 details on CPU context management.
56 initializes/restores the non-secure CPU context as well.
63 #. On receipt of an SMC, save the register context as per `SMCCC`_.
73 PSCI CPU context management
84 The EL3 Runtime Software is responsible for managing register context
117 to CPU context ``cpu_context_t`` data and these are described in
288 - Restores/Initializes the non-secure context and populates the
355 APIs to store and retrieve pointers to this CPU context data. SP-MIN
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| A D | build-options.rst | 160 CPU context. The option must be set to 0 for AArch64-only platforms (that
164 - ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore
165 operations when entering/exiting an EL2 execution context. This is of primary
171 registers to be included when saving and restoring the CPU context. Default
176 execution context. Default value is 0.
180 registers to be included when saving and restoring the CPU context as
659 for saving and restoring the TSP context in this routing model. The
661 interrupts to TSP allowing it to save its context and hand over
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| /tf-a-ffa_el3_spmc/bl1/ |
| A D | bl1.mk | 25 lib/el3_runtime/aarch64/context.S
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| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | xlat-tables-lib-v2-design.rst | 114 context* constitutes the superset of information used by the library to track
121 the default translation context or on an alternative one.
130 ``foo``, the context variable name will be ``foo_xlat_ctx``.
138 Number of translation tables to statically allocate for this context,
142 for this context.
146 Size in bytes of the virtual address space to map using this context. This
153 Size in bytes of the physical address space to map using this context.
155 The default translation context is internally initialized using information
285 the translation tables context affected by them.
289 - **Active context module**
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| A D | secure-partition-manager.rst | 139 restoring) the EL2 system register context before entering (resp.
141 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
482 - Pinned MP SPs: an execution context matches a physical PE. MP SPs must
484 - Migratable UP SPs: a single execution context can run and be migrated on any
487 the single execution context.
548 context of FF-A v1.0.
552 execution context. If the primary boot physical core linear id is N, an MP SP is
585 - Other SPs have their first execution context initialized as a result of secure
801 the PM event is conveyed to the SPMC is implementation-defined in context of
846 translation context.
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| A D | firmware-update.rst | 306 BL1 saves the normal world caller's context, sets the secure image state to
331 context, restores the resuming world's context and returns from exception into
354 restores the normal world context and returns from exception into the normal
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| A D | sdei.rst | 289 context, and mark that the active context.
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| /tf-a-ffa_el3_spmc/lib/psci/ |
| A D | psci_lib.mk | 24 PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S
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| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | interrupt-framework-design.rst | 37 context. It is always handled in Secure-EL1.
41 current execution context. It is always handled in either Non-secure EL1
45 depending upon the security state of the current execution context. It is
195 For example, in Arm GICv3, when the execution context is Secure-EL1/
341 via the context management library APIs.
712 the interrupt, a context switch is required. The following 2 cases
713 require a context switch from secure to non-secure or vice-versa:
784 #. It ensures that the secure CPU context is used to program the next
874 restoring non secure context.
889 #. Restores the secure context by calling
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| /tf-a-ffa_el3_spmc/ |
| A D | PROTOTYPE_README | 193 INFO: Secure Partition context setup start.
198 INFO: S-EL1 SP context on core0 is in 1 state
199 INFO: S-EL1 SP context on core0 is in 0 state
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| /tf-a-ffa_el3_spmc/docs/about/ |
| A D | features.rst | 40 - Secure Monitor library code such as world switching, EL1 context management
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| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 535 - Use sp_boot_info to set SP context
564 - Fixed potential GICD context override with ESPI enabled
864 - Added secondary core endpoint information to the SPMC context
1679 to the context save restore routines
2037 - Refactor xlat context creation
2068 - Fix restoration of PAuth context
2548 - sdei: Missing ``context.h`` header
2791 - Determine client EL from NS context's SCR_EL3
2812 context structure rather than forcing it to 0.
3092 storing EL3 runtime data such as the GICv3 register context.
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