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Searched refs:core (Results 1 – 25 of 73) sorted by relevance

123

/tf-a-ffa_el3_spmc/plat/allwinner/common/
A Dsunxi_cpu_ops.c52 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in sunxi_cpu_off() local
57 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_off()
59 if (core != 0) in sunxi_cpu_off()
64 sunxi_cpu_disable_power(cluster, core); in sunxi_cpu_off()
70 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in sunxi_cpu_on() local
80 BIT(SUNXI_AA64nAA32_OFFSET + core)); in sunxi_cpu_on()
82 sunxi_cpu_enable_power(cluster, core); in sunxi_cpu_on()
90 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_on()
97 unsigned int core; in sunxi_cpu_power_off_others() local
100 for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) { in sunxi_cpu_power_off_others()
[all …]
A Darisc_off.S18 # very ARM core to be turned off.
25 # - Loop until the core in question reaches WFI.
28 # Note that the clamp for core 0 covers more than just the core, activating
58 l.bf 1f # don't touch the bit for core 0
60 l.lwz r5, 0x1500(r13) # core output clamps
65 l.xori r6, r6, -1 # negate core mask
67 l.sw 0x1c30(r13), r5 # ... assert for our core
71 l.slli r6, r6, 2 # r5: core number*4 (0-12)
83 l.movhi r3, 0 # FIXUP! with core mask
88 l.and r5, r5, r3 # mask requested core
[all …]
A Dsunxi_topology.c24 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr() local
29 core >= PLATFORM_MAX_CPUS_PER_CLUSTER) { in plat_core_pos_by_mpidr()
33 return cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core; in plat_core_pos_by_mpidr()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/drivers/pwrc/
A Dhisi_pwrc.c27 #define CPUIDLE_LOCK_ID(core) (0x6 - (core)) argument
311 unsigned int core, in hisi_pdc_set_intmask() argument
318 val |= BIT(core); in hisi_pdc_set_intmask()
320 val &= ~BIT(core); in hisi_pdc_set_intmask()
326 unsigned int core, in hisi_pdc_set_gicmask() argument
333 val |= BIT(core); in hisi_pdc_set_gicmask()
335 val &= ~BIT(core); in hisi_pdc_set_gicmask()
356 BIT(core)); in hisi_pdc_powerup_core()
366 BIT(core)); in hisi_pdc_powerdn_core()
394 BIT(core)); in hisi_powerdn_cluster()
[all …]
A Dhisi_pwrc.h33 void hisi_cpuidle_lock(unsigned int cluster, unsigned int core);
34 void hisi_cpuidle_unlock(unsigned int cluster, unsigned int core);
35 void hisi_set_cpuidle_flag(unsigned int cluster, unsigned int core);
36 void hisi_clear_cpuidle_flag(unsigned int cluster, unsigned int core);
37 void hisi_set_cpu_boot_flag(unsigned int cluster, unsigned int core);
40 void hisi_enter_core_idle(unsigned int cluster, unsigned int core);
43 void hisi_enter_ap_suspend(unsigned int cluster, unsigned int core);
51 void hisi_powerup_core(unsigned int cluster, unsigned int core);
52 void hisi_powerdn_core(unsigned int cluster, unsigned int core);
53 void hisi_powerup_cluster(unsigned int cluster, unsigned int core);
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/ptp3/
A Dmtk_ptp3_main.c38 void ptp3_init(unsigned int core) in ptp3_init() argument
43 if (core < NR_PTP3_CFG1_CPU) { in ptp3_init()
46 ptp3_cfg1[core][PTP3_CFG_ADDR], in ptp3_init()
47 ptp3_cfg1[core][PTP3_CFG_VALUE]); in ptp3_init()
51 if (core >= PTP3_CFG2_CPU_START_ID) { in ptp3_init()
52 _core = core - PTP3_CFG2_CPU_START_ID; in ptp3_init()
63 if (core >= PTP3_CFG3_CPU_START_ID) { in ptp3_init()
75 void ptp3_deinit(unsigned int core) in ptp3_deinit() argument
77 if (core < NR_PTP3_CFG1_CPU) { in ptp3_deinit()
80 ptp3_cfg1[core][PTP3_CFG_ADDR], in ptp3_deinit()
[all …]
A Dmtk_ptp3_common.h45 extern void ptp3_init(unsigned int core);
46 extern void ptp3_deinit(unsigned int core);
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/
A Dhikey960_pm.c69 hisi_set_cpu_boot_flag(cluster, core); in hikey960_pwr_domain_on()
75 hisi_powerup_core(cluster, core); in hikey960_pwr_domain_on()
77 hisi_powerup_cluster(cluster, core); in hikey960_pwr_domain_on()
106 hisi_powerdn_core(cluster, core); in hikey960_pwr_domain_off()
116 hisi_powerdn_cluster(cluster, core); in hikey960_pwr_domain_off()
205 hisi_cpuidle_lock(cluster, core); in hikey960_pwr_domain_suspend()
207 hisi_cpuidle_unlock(cluster, core); in hikey960_pwr_domain_suspend()
212 hisi_enter_core_idle(cluster, core); in hikey960_pwr_domain_suspend()
217 hisi_cpuidle_lock(cluster, core); in hikey960_pwr_domain_suspend()
275 hisi_cpuidle_lock(cluster, core); in hikey960_pwr_domain_suspend_finish()
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/ptp3/
A Dmtk_ptp3_main.c10 #define PTP3_CORE_OFT(core) (0x800 * (core)) argument
31 static void ptp3_init(unsigned int core) in ptp3_init() argument
35 if (core < PTP3_CFG_CPU_START_ID_B) { in ptp3_init()
43 if (core < PTP3_CFG_CPU_START_ID_B) { in ptp3_init()
46 PTP3_CORE_OFT(core); in ptp3_init()
54 PTP3_CORE_OFT(core); in ptp3_init()
65 if (core < PTP3_CFG_CPU_START_ID_B) { in ptp3_init()
124 void ptp3_core_init(unsigned int core) in ptp3_core_init() argument
127 ptp3_init(core); in ptp3_core_init()
129 pdp_init(core, 1); in ptp3_core_init()
[all …]
A Dmtk_ptp3_common.h49 extern void ptp3_core_init(unsigned int core);
50 extern void ptp3_core_unInit(unsigned int core);
/tf-a-ffa_el3_spmc/plat/ti/k3/common/
A Dk3_topology.c29 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr() local
37 core += K3_CLUSTER0_CORE_COUNT; in plat_core_pos_by_mpidr()
39 core += K3_CLUSTER1_CORE_COUNT; in plat_core_pos_by_mpidr()
41 core += K3_CLUSTER2_CORE_COUNT; in plat_core_pos_by_mpidr()
45 return core; in plat_core_pos_by_mpidr()
A Dk3_psci.c44 int core, proc_id, device_id, ret; in k3_pwr_domain_on() local
46 core = plat_core_pos_by_mpidr(mpidr); in k3_pwr_domain_on()
47 if (core < 0) { in k3_pwr_domain_on()
48 ERROR("Could not get target core id: %d\n", core); in k3_pwr_domain_on()
52 proc_id = PLAT_PROC_START_ID + core; in k3_pwr_domain_on()
53 device_id = PLAT_PROC_DEVICE_START_ID + core; in k3_pwr_domain_on()
88 int core, cluster, proc_id, device_id, cluster_id, ret; in k3_pwr_domain_off() local
96 core = plat_my_core_pos(); in k3_pwr_domain_off()
98 proc_id = PLAT_PROC_START_ID + core; in k3_pwr_domain_off()
99 device_id = PLAT_PROC_DEVICE_START_ID + core; in k3_pwr_domain_off()
/tf-a-ffa_el3_spmc/plat/amlogic/g12a/
A Dg12a_pm.c32 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pm_set_reset_addr() local
33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in g12a_pm_set_reset_addr()
40 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pm_reset() local
102 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pwr_domain_on() local
105 if (core == AML_PRIMARY_CPU) { in g12a_pwr_domain_on()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in g12a_pwr_domain_on_finish() local
135 if (core == AML_PRIMARY_CPU) { in g12a_pwr_domain_on_finish()
150 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pwr_domain_off() local
155 if (core == AML_PRIMARY_CPU) in g12a_pwr_domain_off()
167 unsigned int core = plat_calc_core_pos(mpidr); in g12a_pwr_domain_pwr_down_wfi() local
[all …]
/tf-a-ffa_el3_spmc/plat/amlogic/gxl/
A Dgxl_pm.c32 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pm_set_reset_addr() local
33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in gxl_pm_set_reset_addr()
40 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pm_reset() local
102 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pwr_domain_on() local
105 if (core == AML_PRIMARY_CPU) { in gxl_pwr_domain_on()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxl_pwr_domain_on_finish() local
135 if (core == AML_PRIMARY_CPU) { in gxl_pwr_domain_on_finish()
150 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pwr_domain_off() local
155 if (core == AML_PRIMARY_CPU) in gxl_pwr_domain_off()
166 unsigned int core = plat_calc_core_pos(mpidr); in gxl_pwr_domain_pwr_down_wfi() local
[all …]
/tf-a-ffa_el3_spmc/plat/amlogic/gxbb/
A Dgxbb_pm.c32 unsigned int core = plat_calc_core_pos(mpidr); in gxbb_program_mailbox() local
33 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in gxbb_program_mailbox()
87 unsigned int core = plat_calc_core_pos(mpidr); in gxbb_pwr_domain_on() local
90 if (core == AML_PRIMARY_CPU) { in gxbb_pwr_domain_on()
114 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_on_finish() local
119 if (core == AML_PRIMARY_CPU) { in gxbb_pwr_domain_on_finish()
133 unsigned int core = plat_calc_core_pos(mpidr); in gxbb_pwr_domain_off() local
134 uintptr_t addr = AML_PSCI_MAILBOX_BASE + 8 + (core << 4); in gxbb_pwr_domain_off()
142 if (core == AML_PRIMARY_CPU) in gxbb_pwr_domain_off()
152 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_pwr_down_wfi() local
[all …]
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/include/
A Dhisi_ipc.h15 void hisi_ipc_pm_on_off(unsigned int core, unsigned int cluster,
17 void hisi_ipc_pm_suspend(unsigned int core, unsigned int cluster,
19 void hisi_ipc_psci_system_off(unsigned int core, unsigned int cluster);
20 void hisi_ipc_psci_system_reset(unsigned int core, unsigned int cluster,
/tf-a-ffa_el3_spmc/fdts/
A Djuno-ethosn.dtsi17 * Single-core NPU. For multi-core NPU, additional core nodes
21 compatible = "ethosn-core";
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/drivers/ipc/
A Dhisi_ipc.c133 void hisi_ipc_pm_on_off(unsigned int core, unsigned int cluster, in hisi_ipc_pm_on_off() argument
139 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_pm_on_off()
142 cmdpara = IPC_CMD_PARA(0, core); in hisi_ipc_pm_on_off()
147 void hisi_ipc_pm_suspend(unsigned int core, unsigned int cluster, in hisi_ipc_pm_suspend() argument
153 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_pm_suspend()
160 cmdpara = IPC_CMD_PARA(1, core); in hisi_ipc_pm_suspend()
165 void hisi_ipc_psci_system_off(unsigned int core, unsigned int cluster) in hisi_ipc_psci_system_off() argument
170 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_psci_system_off()
178 void hisi_ipc_psci_system_reset(unsigned int core, unsigned int cluster, in hisi_ipc_psci_system_reset() argument
184 enum lpm3_mbox_id mailbox = (enum lpm3_mbox_id)(LPM3_MBX0 + core); in hisi_ipc_psci_system_reset()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dnvg.c204 int32_t nvg_online_core(uint32_t ari_base, uint32_t core) in nvg_online_core() argument
213 if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) { in nvg_online_core()
214 ERROR("%s: unsupported core id (%d)\n", __func__, core); in nvg_online_core()
220 if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) { in nvg_online_core()
221 ERROR("%s: unknown core id (%d)\n", __func__, core); in nvg_online_core()
226 ((uint64_t)core & MCE_CORE_ID_MASK)); in nvg_online_core()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/include/
A Dhisi_pwrc.h13 void hisi_pwrc_set_core_bx_addr(unsigned int core,
16 void hisi_pwrc_enable_debug(unsigned int core,
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/
A Dhisi_pwrc.c25 void hisi_pwrc_set_core_bx_addr(unsigned int core, unsigned int cluster, in hisi_pwrc_set_core_bx_addr() argument
36 i = cluster * CLUSTER_CORE_COUNT + core; in hisi_pwrc_set_core_bx_addr()
55 void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster) in hisi_pwrc_enable_debug() argument
59 enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster); in hisi_pwrc_enable_debug()
/tf-a-ffa_el3_spmc/docs/design/
A Dpsci-pd-tree.rst36 #. The attributes of a core power domain differ from the attributes of power
39 performing a power management operation on the core power domain.
125 unique number (core index) between ``0`` and ``PLAT_CORE_COUNT - 1`` to each core
129 ``plat_core_pos_by_mpidr(mpidr)`` will return the core index for the core
141 for a core domain will be the same as the index returned by
143 relationship allows the core nodes to be allocated in a separate array
145 core in the array is the same as the return value from these APIs.
158 used by the platform is not equal to the number of core power domains.
173 allow use of a simpler logic to convert an MPIDR to a core index.
175 Traversing through and distinguishing between core and non-core power domains
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/
A Dplat_pm.c34 struct core_context core[PLATFORM_MAX_CPUS_PER_CLUSTER]; member
59 return &cluster->core[cpuid]; in cluster_core()
151 struct core_context *core; in mt_cpu_save() local
153 core = get_core_data(mpidr); in mt_cpu_save()
154 mt_save_generic_timer(core->timer_data); in mt_cpu_save()
162 struct core_context *core; in mt_cpu_restore() local
164 core = get_core_data(mpidr); in mt_cpu_restore()
165 mt_restore_generic_timer(core->timer_data); in mt_cpu_restore()
/tf-a-ffa_el3_spmc/plat/amlogic/axg/
A Daxg_pm.c31 unsigned int core = plat_calc_core_pos(mpidr); in axg_pm_set_reset_addr() local
32 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); in axg_pm_set_reset_addr()
39 unsigned int core = plat_calc_core_pos(mpidr); in axg_pm_reset() local
40 uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; in axg_pm_reset()
/tf-a-ffa_el3_spmc/docs/plat/
A Dimx8.rst5 performance-scalable multi-core platform that includes single-,
6 dual-, and quad-core families based on the Arm® Cortex®
12 The i.MX8QM is with 2 Cortex-A72 ARM core, 4 Cortex-A53 ARM core
15 The i.MX8QX is with 4 Cortex-A35 ARM core and 1 Cortex-M4 system

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