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Searched refs:cs (Results 1 – 23 of 23) sorted by relevance

/tf-a-ffa_el3_spmc/plat/marvell/armada/common/
A Dmarvell_ddr_info.c15 #define DRAM_CH0_MMAP_LOW_REG(iface, cs, base) \ argument
17 #define DRAM_CH0_MMAP_HIGH_REG(iface, cs, base) \ argument
18 (DRAM_CH0_MMAP_LOW_REG(iface, cs, base) + 4)
29 #define DRAM_CS_ENABLED(iface, cs, base) \ argument
30 (mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \
32 #define GET_DRAM_REGION_SIZE_CODE(iface, cs, base) \ argument
81 uint8_t cs, iface; in mvebu_get_dram_size() local
84 for (cs = 0; cs < DRAM_MAX_CS_NUM; cs++) { in mvebu_get_dram_size()
87 if (!DRAM_CS_ENABLED(iface, cs, ap_base_addr)) in mvebu_get_dram_size()
94 GET_DRAM_REGION_SIZE_CODE(iface, cs, in mvebu_get_dram_size()
[all …]
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2160aqds/
A Dddr_init.c27 .cs[0].bnds = U(0x03FF),
28 .cs[1].bnds = U(0x03FF),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
33 .cs[2].config = U(0x00),
34 .cs[3].config = U(0x00),
78 .cs[0].bnds = U(0x03FF),
82 .cs[2].bnds = U(0x00),
83 .cs[3].bnds = U(0x00),
133 .cs[2].bnds = U(0x00),
[all …]
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2162aqds/
A Dddr_init.c27 .cs[0].bnds = U(0x03FFU),
28 .cs[1].bnds = U(0x03FF),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
33 .cs[2].config = U(0x00),
34 .cs[3].config = U(0x00),
78 .cs[0].bnds = U(0x03FF),
82 .cs[2].bnds = U(0x00),
83 .cs[3].bnds = U(0x00),
133 .cs[2].bnds = U(0x00),
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/common/ddr/ddr_b/
A Dboot_init_dram.c2340 uint32_t ch, cs; in dbsc_regset_post() local
2347 for (cs = 0; cs < CS_CNT; cs++) { in dbsc_regset_post()
2352 cs); in dbsc_regset_post()
2390 for (cs = 0; cs < CS_CNT; cs++) { in dbsc_regset_post()
3418 for (cs = 0; cs < CS_CNT; cs++) { in wdqdm_man1()
4107 for (cs = 0; cs < CS_CNT; cs++) { in adjust_wpath_latency()
4110 cs); in adjust_wpath_latency()
4133 uint32_t ch, cs; in rcar_dram_init() local
4224 for (cs = 0; cs < CS_CNT; cs++) { in rcar_dram_init()
4229 for (cs = 0; cs < CS_CNT; cs++) in rcar_dram_init()
[all …]
A Dboot_init_dram_regdef.h31 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) argument
/tf-a-ffa_el3_spmc/lib/debugfs/
A Ddevfip.c191 chan_t cs; in fipread() local
208 if (clone(fip->c, &cs) == NULL) { in fipread()
226 if (devtab[cs.index]->seek(&cs, off, KSEEK_SET) < 0) { in fipread()
230 n = devtab[cs.index]->read(&cs, buf, n); in fipread()
/tf-a-ffa_el3_spmc/drivers/nxp/ddr/nxp-ddr/
A Dddrc.c221 (regs->cs[i].bnds & U(0xfffefffe)) >> 1U); in ddrc_set_regs()
223 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds); in ddrc_set_regs()
405 (regs->cs[i].config & ~CTLR_INTLV_MASK)); in ddrc_set_regs()
407 ddr_out32(&ddr->csn_cfg[i], regs->cs[i].config); in ddrc_set_regs()
456 if ((regs->cs[i].config & 0x80000000) == 0) { in ddrc_set_regs()
460 ((regs->cs[i].config >> 14) & 0x3) + 2 + in ddrc_set_regs()
461 ((regs->cs[i].config >> 8) & 0x7) + 12 + in ddrc_set_regs()
462 ((regs->cs[i].config >> 4) & 0x3) + 0 + in ddrc_set_regs()
463 ((regs->cs[i].config >> 0) & 0x7) + 8 + in ddrc_set_regs()
503 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds); in ddrc_set_regs()
[all …]
A Dregs.c59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) | in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
903 regs->cs[i].bnds = ((sa & 0xffff) << 16) | in cal_ddr_csn_bnds()
908 regs->cs[i].bnds = 0xffffffff; in cal_ddr_csn_bnds()
920 const unsigned int cs0_config = regs->cs[0].config; in cal_ddr_addr_dec()
925 unsigned int cs; in cal_ddr_addr_dec() local
953 cs = 1; in cal_ddr_addr_dec()
956 cs = 2; in cal_ddr_addr_dec()
959 cs = 0; in cal_ddr_addr_dec()
1003 if (cs != 0U) { in cal_ddr_addr_dec()
[all …]
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2160ardb/
A Dddr_init.c26 .cs[0].config = U(0xA8050322),
27 .cs[1].config = U(0x80000322),
28 .cs[0].bnds = U(0x3FF),
29 .cs[1].bnds = U(0x3FF),
/tf-a-ffa_el3_spmc/drivers/mtd/spi-mem/
A Dspi_mem.c26 unsigned int cs; member
163 ret = ops->claim_bus(spi_slave.cs); in spi_mem_exec_op()
216 spi_slave.cs = fdt32_to_cpu(*cuint); in spi_mem_init_slave()
/tf-a-ffa_el3_spmc/include/drivers/
A Dspi_mem.h94 int (*claim_bus)(unsigned int cs);
/tf-a-ffa_el3_spmc/drivers/brcm/spi/
A Diproc_qspi.h100 int iproc_qspi_setup(uint32_t bus, uint32_t cs,
A Diproc_qspi.c29 int iproc_qspi_setup(uint32_t bus, uint32_t cs, uint32_t max_hz, uint32_t mode) in iproc_qspi_setup() argument
/tf-a-ffa_el3_spmc/drivers/renesas/common/
A Dddr_regs.h16 #define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) argument
/tf-a-ffa_el3_spmc/drivers/st/fmc/
A Dstm32_fmc2_nand.c149 struct stm32_fmc2_cs_reg cs[MAX_CS]; member
570 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; in stm32_fmc2_read_data()
617 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; in stm32_fmc2_write_data()
707 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base, in stm32_fmc2_exec()
712 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base, in stm32_fmc2_exec()
865 stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) + in stm32_fmc2_init()
872 stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) + in stm32_fmc2_init()
879 stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) + in stm32_fmc2_init()
/tf-a-ffa_el3_spmc/include/drivers/nxp/ddr/
A Dddr.h54 } cs[MAX_CS_NUM]; member
/tf-a-ffa_el3_spmc/drivers/st/spi/
A Dstm32_qspi.c340 static int stm32_qspi_claim_bus(unsigned int cs) in stm32_qspi_claim_bus() argument
344 if (cs >= QSPI_MAX_CHIP) { in stm32_qspi_claim_bus()
350 if (cs == 1U) { in stm32_qspi_claim_bus()
/tf-a-ffa_el3_spmc/plat/intel/soc/common/drivers/qspi/
A Dcadence_qspi.c99 int cad_qspi_stig_cmd_helper(int cs, uint32_t cmd) in cad_qspi_stig_cmd_helper() argument
106 & CAD_QSPI_CFG_CS_MSK) | CAD_QSPI_CFG_CS(cs)); in cad_qspi_stig_cmd_helper()
500 void cad_qspi_set_chip_select(int cs) in cad_qspi_set_chip_select() argument
502 cad_qspi_cs = cs; in cad_qspi_set_chip_select()
A Dcadence_qspi.h171 void cad_qspi_set_chip_select(int cs);
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/dram/
A Ddram_spec_timing.c130 uint32_t cs, ch; in get_max_die_capability() local
133 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { in get_max_die_capability()
136 dram_info[ch].per_die_capability[cs]); in get_max_die_capability()
A Ddfs.c82 uint8_t channel, uint8_t cs) in get_cs_die_capability() argument
91 row = cs == 0 ? ch->cs0_row : ch->cs1_row; in get_cs_die_capability()
/tf-a-ffa_el3_spmc/services/std_svc/spm/spmc/
A Dspmc_main.c146 unsigned int cs; in spmc_smc_return() local
148 cs = is_caller_secure(flags); in spmc_smc_return()
155 else if (cs && ffa_is_secure_world_id(FFA_RECEIVER(x1))) { in spmc_smc_return()
159 else if (!cs && ffa_is_secure_world_id(FFA_RECEIVER(x1))) { in spmc_smc_return()
/tf-a-ffa_el3_spmc/drivers/nxp/ddr/phy-gen2/
A Dphy.c2517 if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0U) { in compute_ddr_phy()
2520 odt_rd = (regs->cs[i].config >> 20U) & U(0x7); in compute_ddr_phy()
2521 odt_wr = (regs->cs[i].config >> 16U) & U(0x7); in compute_ddr_phy()

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