Searched refs:cycle (Results 1 – 8 of 8) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/m0/src/
A D	stopwatch.c	32 unsigned int cycle; in stopwatch_set_usecs() local 36 cycle = US_TO_CYCLE(usecs); in stopwatch_set_usecs() 37 mmio_write_32(SYST_RVR, cycle); in stopwatch_set_usecs()
/tf-a-ffa_el3_spmc/docs/perf/
A D	performance-monitoring-unit.rst	22 - A dedicated cycle counter: ``PMCCNTR``. 47 configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has 127 - If set to ``1`` enables the cycle counter ``PMCCNTR``. 134 - If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
/tf-a-ffa_el3_spmc/docs/process/
A D	security-hardening.rst	85 - ``SCCD`` for the cycle counter. 92 - Prohibit general event counters and the cycle counter: 109 - Prohibit cycle counter: ``MDCR_EL3.SPME == 0 && PMCR_EL0.DP == 1``. 115 - Prohibit cycle counter: ``MDCR_EL3.SCCD == 1``
A D	platform-compatibility-policy.rst	26 interface will be removed. This must be at least 1 full release cycle in future.
/tf-a-ffa_el3_spmc/docs/security_advisories/
A D	security-advisory-tfv-5.rst	32 bit is set to zero, the cycle counter (when enabled) counts during secure world
/tf-a-ffa_el3_spmc/docs/threat_model/
A D	threat_model_spm.rst	41 - Focus on the run-time part of the life-cycle (no specific emphasis on boot
A D	threat_model.rst	756 | | events and cycle counting in the Secure world is |
/tf-a-ffa_el3_spmc/docs/
A D	change-log.rst	2009 setting rev.0.35, qos: change subslot cycle, Change periodic write DQ training option. 2129 and cycle counting gets disabled by setting PMCR.DP bit. 2134 and cycle counting gets disabled by setting PMCR_EL0.DP bit. 3141 - Control register PMCR_EL0 / PMCR is set to prohibit cycle counting in the

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