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/tf-a-ffa_el3_spmc/drivers/nxp/ddr/phy-gen1/
A Dphy.c25 debug("clk_cntl = 0x%x\n", regs->clk_cntl); in cal_ddr_sdram_clk_cntl()
33 debug("cdr[0] = 0x%x\n", regs->cdr[0]); in cal_ddr_cdr()
34 debug("cdr[1] = 0x%x\n", regs->cdr[1]); in cal_ddr_cdr()
73 regs->debug[2] = U(0x00000400); in cal_ddr_dbg()
74 regs->debug[4] = U(0xff800800); in cal_ddr_dbg()
75 regs->debug[5] = U(0x08000800); in cal_ddr_dbg()
76 regs->debug[6] = U(0x08000800); in cal_ddr_dbg()
77 regs->debug[7] = U(0x08000800); in cal_ddr_dbg()
78 regs->debug[8] = U(0x08000800); in cal_ddr_dbg()
81 regs->debug[28] = popts->cpo_sample; in cal_ddr_dbg()
[all …]
/tf-a-ffa_el3_spmc/drivers/nxp/ddr/nxp-ddr/
A Ddimm.c167 debug("n_ranks %d\n", pdimm->n_ranks); in cal_dimm_params()
251 debug("rdimm %d\n", pdimm->rdimm); in cal_dimm_params()
253 debug("rc 0x%x\n", pdimm->rc); in cal_dimm_params()
321 debug("taa_ps %d\n", pdimm->taa_ps); in cal_dimm_params()
327 debug("trcd_ps %d\n", pdimm->trcd_ps); in cal_dimm_params()
333 debug("trp_ps %d\n", pdimm->trp_ps); in cal_dimm_params()
338 debug("tras_ps %d\n", pdimm->tras_ps); in cal_dimm_params()
343 debug("trc_ps %d\n", pdimm->trc_ps); in cal_dimm_params()
347 debug("trfc1_ps %d\n", pdimm->trfc1_ps); in cal_dimm_params()
357 debug("tfaw_ps %d\n", pdimm->tfaw_ps); in cal_dimm_params()
[all …]
A Dddr.c301 debug("cs %d\n", i); in cal_odt()
303 debug(" odt_rd_cfg 0x%x\n", in cal_odt()
306 debug(" odt_wr_cfg 0x%x\n", in cal_odt()
312 debug(" odt_rtt_wr 0x%x\n", in cal_odt()
533 debug("Controller %d\n", i); in parse_spd()
535 debug("DIMM %d\n", j); in parse_spd()
544 debug("addr 0x%x\n", addr); in parse_spd()
618 debug("cal cs\n"); in parse_spd()
700 debug("CS %d\n", i); in assign_intlv_addr()
761 debug("CS %d\n", i); in assign_non_intlv_addr()
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A Dddrc.c326 if (regs->debug[i] != 0) { in ddrc_set_regs()
332 ddr_out32(&ddr->debug[i], regs->debug[i]); in ddrc_set_regs()
363 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
368 if (regs->debug[28] != 0) { in ddrc_set_regs()
370 tmp |= regs->debug[28] & 0xff; in ddrc_set_regs()
374 ddr_out32(&ddr->debug[28], tmp); in ddrc_set_regs()
380 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
561 tmp = ddr_in32(&ddr->debug[13]); in ddrc_set_regs()
567 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
568 debug("debug[28] 0x%x\n", tmp); in ddrc_set_regs()
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A Dregs.c69 debug("cs%d\n", i); in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
321 debug("PAR_LAT = 0x%x\n", par_lat); in cal_timing_cfg()
519 debug("interval = 0x%x\n", regs->interval); in cal_ddr_sdram_interval()
845 debug("dq_map[0] = 0x%x\n", regs->dq_map[0]); in cal_ddr_dq_mapping()
846 debug("dq_map[1] = 0x%x\n", regs->dq_map[1]); in cal_ddr_dq_mapping()
863 debug("zq_cntl = 0x%x\n", regs->zq_cntl); in cal_ddr_zq_cntl()
881 debug("eor = 0x%x\n", regs->eor); in cal_ddr_eor()
983 debug("cacheline size %d\n", cacheline); in cal_ddr_addr_dec()
1140 debug("dec[%d] = 0x%x\n", i, regs->dec[i]); in cal_ddr_addr_dec()
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A Dutility.c118 debug("%s: nothing to do.\n", __func__); in disable_unused_ddrc()
136 debug("valid_spd_mask = 0x%x\n", valid_spd_mask); in disable_unused_ddrc()
147 debug("Disable first DDR controller\n"); in disable_unused_ddrc()
153 debug("Disable second DDR controller\n"); in disable_unused_ddrc()
163 debug("Both controllers in use.\n"); in disable_unused_ddrc()
174 debug("Setting HN-F node %d\n", i); in disable_unused_ddrc()
175 debug("nodeid = 0x%x\n", nodeid); in disable_unused_ddrc()
/tf-a-ffa_el3_spmc/drivers/marvell/comphy/
A Dphy-comphy-common.h15 #define debug(format...) printf(format) macro
17 #define debug(format, arg...) macro
147 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ", in reg_set()
149 debug("old value = 0x%x ==> ", mmio_read_32(addr)); in reg_set()
152 debug("new val 0x%x\n", mmio_read_32(addr)); in reg_set()
159 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ", in reg_set16()
161 debug("old value = 0x%x ==> ", mmio_read_16(addr)); in reg_set16()
164 debug("new val 0x%x\n", mmio_read_16(addr)); in reg_set16()
A Dphy-comphy-cp110.c408 debug("stage: Comphy configuration\n"); in mvebu_cp110_comphy_sata_power_on()
822 debug("stage: RF Reset\n"); in mvebu_cp110_comphy_sgmii_power_on()
1234 debug("stage: RF Reset\n"); in mvebu_cp110_comphy_xfi_power_on()
1327 debug("On lane %d\n", comphy_index); in mvebu_cp110_comphy_pcie_power_on()
1662 debug("stage: Comphy power up\n"); in mvebu_cp110_comphy_pcie_power_on()
1725 debug("stage: Check PLL\n"); in mvebu_cp110_comphy_pcie_power_on()
1920 debug("stage: RF Reset\n"); in mvebu_cp110_comphy_rxaui_power_on()
2058 debug("stage: Comphy power up\n"); in mvebu_cp110_comphy_usb3_power_on()
2065 debug("stage: Check PLL\n"); in mvebu_cp110_comphy_usb3_power_on()
2091 debug("rx_training preparation\n\n"); in rx_pre_train()
[all …]
/tf-a-ffa_el3_spmc/docs/security_advisories/
A Dsecurity-advisory-tfv-2.rst5 | Title | Enabled secure self-hosted invasive debug interface can |
25 The ``MDCR_EL3.SDD`` bit controls AArch64 secure self-hosted invasive debug
28 entrypoint code, which enables debug exceptions from the secure world. This can
31 by saving and restoring the appropriate debug registers), this may allow a
34 The ``MDCR_EL3.SDD`` bit should be assigned to ``1`` to disable debug exceptions
42 secure self-hosted invasive debug enablement. TF assigns these bits to ``00``
43 meaning that debug exceptions from Secure EL1 are enabled by the authentication
45 secure privileged invasive debug is enabled by the authentication interface, at
48 However, given that TF contains no support for handling debug exceptions, the
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
/tf-a-ffa_el3_spmc/drivers/nxp/ddr/phy-gen2/
A Dphy.c1883 debug("Initialize PHY %d config\n", i); in c_init_phy_config()
2043 debug("End of initialization\n"); in wait_fw_done()
2084 debug("/tDWL, MREP, MRD and MWD\n"); in wait_fw_done()
2088 debug("End of CA training\n"); in wait_fw_done()
2100 debug("Timed out\n"); in wait_fw_done()
2560 debug("Initializing message block\n"); in compute_ddr_phy()
2588 debug("Load 1D firmware\n"); in compute_ddr_phy()
2597 debug("Execute firmware\n"); in compute_ddr_phy()
2618 debug("Load 2D firmware\n"); in compute_ddr_phy()
2627 debug("Execute 2D firmware\n"); in compute_ddr_phy()
[all …]
/tf-a-ffa_el3_spmc/drivers/marvell/secure_dfx_access/
A Dmisc_dfx.c17 #define debug(format...) NOTICE(format) macro
19 #define debug(format, arg...) macro
108 debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val); in mvebu_dfx_misc_handle()
A Darmada_thermal.c17 #define debug(format...) NOTICE(format) macro
19 #define debug(format, arg...) macro
212 debug("thermal: Initialization done\n"); in armada_ap806_thermal_init()
/tf-a-ffa_el3_spmc/include/drivers/nxp/ddr/
A Dddr.h36 #define debug(...) INFO(__VA_ARGS__) macro
38 #define debug(...) VERBOSE(__VA_ARGS__) macro
75 unsigned int debug[64]; member
A Dimmap.h123 unsigned int debug[64]; /* debug_1 to debug_64 */ member
/tf-a-ffa_el3_spmc/plat/marvell/armada/common/
A Dmrvl_sip_svc.c25 #define debug(format...) NOTICE(format) macro
27 #define debug(format, arg...) macro
85 debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n", in mrvl_sip_smc_handler()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/
A Dtegra_common.mk42 ${TEGRA_LIBS}/debug/profiler.c \
44 ${TEGRA_LIBS}/debug/profiler.c \
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2160ardb/
A Dddr_init.c177 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
178 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
179 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
/tf-a-ffa_el3_spmc/docs/plat/
A Dwarp7.rst80 …ot/u-boot.cfgout -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.…
90 tools/cert_create/cert_create -n --rot-key "build/warp7/debug/rot_key.pem" \
94 --tb-fw=build/warp7/debug/bl2.bin \
176 …oot.cfgout.warp7 -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.…
179 cp build/warp7/debug/bl2.bin.imx ${TEMP}
A Dintel-agilex.rst73 NOTICE: BL2: v2.1(debug)
79 NOTICE: BL31: v2.1(debug)
A Dintel-stratix10.rst74 NOTICE: BL2: v2.0(debug):v2.0-809-g7f8474a-dirty
86 NOTICE: BL31: v2.0(debug):v2.0-810-g788c436-dirty
/tf-a-ffa_el3_spmc/tools/fiptool/
A DMakefile.msvc23 $(LD) /nologo /INCREMENTAL:NO /debug /nodefaultlib:libc.lib /out:$@ $(LIBS) $**
/tf-a-ffa_el3_spmc/docs/getting_started/
A Dtools-build.rst84 build/<platform>/debug/fip.bin
98 --tb-fw build/<platform>/debug/fip.bin
131 ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
151 ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2160aqds/
A Dddr_init.c312 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
313 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
314 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/lx2162aqds/
A Dddr_init.c312 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
313 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
314 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
/tf-a-ffa_el3_spmc/docs/threat_model/
A Dthreat_model.rst52 | ``DF2`` | | TF-A log system framework outputs debug messages |
125 | ``AppDebug`` | | Physical attacker using debug signals to access |
442 | | debug builds by default. Alternatively, the log |
453 | | debug and trace interface** |
455 | | | Arm processors include hardware-assisted debug |
484 | ``Mitigations`` | | Configuration of debug and trace capabilities is |
486 | | disable the debug and trace capability for |
487 | | production releases or enable proper debug |
759 | | event counting depends on external debug interface|
761 | | enabled if external debug is enabled. |
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