Searched refs:elr_el3 (Results 1 – 22 of 22) sorted by relevance
| /tf-a-ffa_el3_spmc/bl32/tsp/ |
| A D | tsp_interrupt.c | 29 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) in tsp_update_sync_sel1_intr_stats() argument
40 read_mpidr(), elr_el3); in tsp_update_sync_sel1_intr_stats()
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| A D | tsp_private.h | 100 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/drivers/ |
| A D | tegra_gic.h | 17 uint64_t elr_el3; member
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/ |
| A D | tegra_fiq_glue.c | 66 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); in tegra_fiq_interrupt_handler()
139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
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| /tf-a-ffa_el3_spmc/services/std_svc/sdei/ |
| A D | sdei_intr_mgmt.c | 38 uint64_t elr_el3; member
174 disp_ctx->elr_el3 = read_ctx_reg(tgt_el3, CTX_ELR_EL3); in save_event_ctx()
194 write_ctx_reg(tgt_el3, CTX_ELR_EL3, disp_ctx->elr_el3); in restore_event_ctx()
328 SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3); in setup_ns_dispatch()
734 write_elr_el2(disp_ctx->elr_el3); in sdei_event_complete()
738 write_elr_el1(disp_ctx->elr_el3); in sdei_event_complete()
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| /tf-a-ffa_el3_spmc/bl2/aarch64/ |
| A D | bl2_el3_entrypoint.S | 99 msr elr_el3, x0
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| /tf-a-ffa_el3_spmc/lib/cpus/aarch64/ |
| A D | wa_cve_2017_5715_bpiall.S | 58 mrs x7, elr_el3
85 msr elr_el3, x11
277 msr elr_el3, x7
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| A D | neoverse_n1.S | 646 mrs x3, elr_el3
648 msr elr_el3, x3
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| /tf-a-ffa_el3_spmc/bl31/aarch64/ |
| A D | runtime_exceptions.S | 222 mrs x1, elr_el3
498 mrs x17, elr_el3
590 mrs x4, elr_el3
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| A D | ea_delegate.S | 246 mrs x3, elr_el3
299 msr elr_el3, x2
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| A D | crash_reporting.S | 399 mrs x15, elr_el3
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| /tf-a-ffa_el3_spmc/plat/qti/qtiseclib/inc/ |
| A D | qtiseclib_defs.h | 77 uint64_t elr_el3; member
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| /tf-a-ffa_el3_spmc/bl1/aarch64/ |
| A D | bl1_exceptions.S | 182 msr elr_el3, x0
271 mrs x17, elr_el3
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| /tf-a-ffa_el3_spmc/plat/nxp/common/sip_svc/aarch64/ |
| A D | sipsvc.S | 56 msr elr_el3, x1
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| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey/aarch64/ |
| A D | hikey_helpers.S | 117 mrs x4, elr_el3
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| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/aarch64/ |
| A D | hikey960_helpers.S | 121 mrs x4, elr_el3
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| /tf-a-ffa_el3_spmc/plat/qti/qtiseclib/src/ |
| A D | qtiseclib_cb_interface.c | 138 qti_ns_ctx->elr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_ELR_EL3); in qtiseclib_cb_get_ns_ctx()
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| /tf-a-ffa_el3_spmc/plat/renesas/common/aarch64/ |
| A D | plat_helpers.S | 190 msr elr_el3, x0
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| /tf-a-ffa_el3_spmc/include/arch/aarch64/ |
| A D | arch_helpers.h | 262 DEFINE_SYSREG_RW_FUNCS(elr_el3) in DEFINE_SYSREG_READ_FUNC()
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| /tf-a-ffa_el3_spmc/lib/el3_runtime/aarch64/ |
| A D | context.S | 902 msr elr_el3, x17
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| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | interrupt-framework-design.rst | 788 now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
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| A D | firmware-design.rst | 1224 elr_el3 = 0x0000000088000114
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