Searched refs:group (Results 1 – 15 of 15) sorted by relevance
| /tf-a-ffa_el3_spmc/docs/resources/diagrams/plantuml/ |
| A D | io_dev_registration.puml | 10 group io dev registration
51 end group
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| A D | io_dev_init_and_check.puml | 8 group init and check device (image_id)
61 end group
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| /tf-a-ffa_el3_spmc/docs/design_documents/ |
| A D | cmake_framework.rst | 68 The related parameters shall be packed into a group (or "setting group"). The
81 the previous section. A group can be applied onto a target, i.e. a collection of
125 First, we create a setting group called *mem_conf* and fill it with several
130 Next, we create a target called *fw1* and add the *mem_conf* setting group to
132 the parameters declared in the setting group. Then we set the target type to
134 the settings group, we can use it for conditionally adding source files. E.g.
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| /tf-a-ffa_el3_spmc/tools/memory/ |
| A D | print_memory_map.py | 57 address_list.append([match.group(0), symbol, image])
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/ |
| A D | plat_ras.c | 430 #define ADD_ONE_ERR_GROUP(errselr_start, group) \ argument
431 ERR_RECORD_SYSREG_V1((errselr_start), (uint32_t)ARRAY_SIZE((group)), \
433 &tegra194_ras_record_handler, (group))
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| /tf-a-ffa_el3_spmc/plat/imx/common/include/sci/svc/misc/ |
| A D | sci_misc_api.h | 190 sc_misc_dma_group_t group);
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| /tf-a-ffa_el3_spmc/plat/imx/common/sci/svc/misc/ |
| A D | misc_rpc_clnt.c | 93 sc_misc_dma_group_t group) in sc_misc_set_dma_group() argument
102 RPC_U8(&msg, 2U) = (uint8_t)group; in sc_misc_set_dma_group()
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| /tf-a-ffa_el3_spmc/lib/romlib/ |
| A D | romlib_generator.py | 254 mapping = {"jmptbl_address": matching_symbol.group(1)}
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| /tf-a-ffa_el3_spmc/docs/getting_started/ |
| A D | porting-guide.rst | 569 This mask reflects the set of group counters that should be enabled. The
570 maximum number of group 1 counters supported by AMUv1 is 16 so the mask
571 can be at most 0xffff. If the platform does not define this mask, no group 1
2111 *power domain*. A *power domain* is a CPU or a logical group of CPUs which
2120 CPUs (for example, a cluster), and level 2 is a group of clusters (for
2635 ``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2675 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2676 Register* is read to determine the id of the group 1 interrupt. This id
2682 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
2709 group 1*. The read changes the state of the highest pending interrupt from
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| A D | rt-svc-writers-guide.rst | 20 independent implementation of services for each group, which are then compiled
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| A D | build-options.rst | 25 - ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
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| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | platform-interrupt-controller-API.rst | 179 assign the interrupt to the right group.
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| A D | exception-handling.rst | 532 interrupts. This programs the appropriate priority and group (Group 0) on
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| /tf-a-ffa_el3_spmc/docs/process/ |
| A D | coding-style.rst | 370 Within each group, ``#include`` statements must be in alphabetical order,
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| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | firmware-design.rst | 1319 (priority, group, configuration). Each element of the array shall be populated
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