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/tf-a-ffa_el3_spmc/plat/nxp/common/soc_errata/
A Derrata_a050426.c21 for (i = 0U; i < 4U; i++) { in erratum_a050426()
30 for (i = 0U; i < 3U; i++) { in erratum_a050426()
35 for (i = 0U; i < 2U; i++) { in erratum_a050426()
38 for (i = 0U; i < 3U; i++) { in erratum_a050426()
42 for (i = 0U; i < 4U; i++) { in erratum_a050426()
58 for (i = 0U; i < 3U; i++) { in erratum_a050426()
62 for (i = 0U; i < 2U; i++) { in erratum_a050426()
68 for (i = 0U; i < 4U; i++) { in erratum_a050426()
72 for (i = 0U; i < 2U; i++) { in erratum_a050426()
76 for (i = 0U; i < 4U; i++) { in erratum_a050426()
[all …]
/tf-a-ffa_el3_spmc/drivers/nxp/flexspi/nor/
A Dtest_fspi.c31 uint32_t failed, i; in fspi_test() local
43 for (i = 0; i < size; i++) in fspi_test()
50 NOTICE("[%d]: Success Erase: data in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]); in fspi_test()
52 ERROR("Erase: Failed -->xxx with buffer[%d]=0x%08x\n", i, buffer[i]); in fspi_test()
55 for (i = 0; i < SIZE_BUFFER; i++) in fspi_test()
56 buffer[i] = 0x12345678; in fspi_test()
63 for (i = 0; i < size; i++) in fspi_test()
70 NOTICE("[%d]: Success IpWrite with IP READ in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]); in fspi_test()
72 ERROR("Write: Failed -->xxxx with IP READ in buffer[%d]=0x%08x\n", i, buffer[i]); in fspi_test()
79 for (i = 0; i < size; i++) in fspi_test()
[all …]
/tf-a-ffa_el3_spmc/plat/intel/soc/stratix10/soc/
A Ds10_pinmux.c190 unsigned int i; in config_pinmux() local
192 for (i = 0; i < 96; i += 2) { in config_pinmux()
194 hoff_ptr->pinmux_sel_array[i], in config_pinmux()
195 hoff_ptr->pinmux_sel_array[i+1]); in config_pinmux()
198 for (i = 0; i < 96; i += 2) { in config_pinmux()
200 hoff_ptr->pinmux_io_array[i], in config_pinmux()
201 hoff_ptr->pinmux_io_array[i+1]); in config_pinmux()
204 for (i = 0; i < 42; i += 2) { in config_pinmux()
206 hoff_ptr->pinmux_fpga_array[i], in config_pinmux()
207 hoff_ptr->pinmux_fpga_array[i+1]); in config_pinmux()
[all …]
/tf-a-ffa_el3_spmc/plat/intel/soc/agilex/soc/
A Dagilex_pinmux.c197 unsigned int i; in config_pinmux() local
199 for (i = 0; i < 96; i += 2) { in config_pinmux()
201 hoff_ptr->pinmux_sel_array[i], in config_pinmux()
202 hoff_ptr->pinmux_sel_array[i+1]); in config_pinmux()
205 for (i = 0; i < 96; i += 2) { in config_pinmux()
207 hoff_ptr->pinmux_io_array[i], in config_pinmux()
208 hoff_ptr->pinmux_io_array[i+1]); in config_pinmux()
211 for (i = 0; i < 42; i += 2) { in config_pinmux()
213 hoff_ptr->pinmux_fpga_array[i], in config_pinmux()
214 hoff_ptr->pinmux_fpga_array[i+1]); in config_pinmux()
[all …]
/tf-a-ffa_el3_spmc/plat/nxp/common/setup/
A Dls_common.c63 int i = 0; in mmap_add_ddr_regions_statically() local
72 info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
73 info_dram_regions->region[i].size, in mmap_add_ddr_regions_statically()
89 (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
96 for (i = 1; i < info_dram_regions->num_dram_regions; i++) { in mmap_add_ddr_regions_statically()
116 int i = 0; in mmap_add_ddr_region_dynamically() local
125 info_dram_regions->region[i].addr, in mmap_add_ddr_region_dynamically()
126 info_dram_regions->region[i].size, in mmap_add_ddr_region_dynamically()
149 for (i = 1; i < info_dram_regions->num_dram_regions; i++) { in mmap_add_ddr_region_dynamically()
252 unsigned int i; in get_cluster_info() local
[all …]
/tf-a-ffa_el3_spmc/plat/arm/common/fconf/
A Dfconf_sdei_getter.c13 #define PRIVATE_EVENT_NUM(i) private_events[3 * (i)] argument
14 #define PRIVATE_EVENT_INTR(i) private_events[3 * (i) + 1] argument
15 #define PRIVATE_EVENT_FLAGS(i) private_events[3 * (i) + 2] argument
17 #define SHARED_EVENT_NUM(i) shared_events[3 * (i)] argument
18 #define SHARED_EVENT_INTR(i) shared_events[3 * (i) + 1] argument
19 #define SHARED_EVENT_FLAGS(i) shared_events[3 * (i) + 2] argument
25 uint32_t i; in fconf_populate_sdei_dyn_config() local
64 for (i = 0; i < sdei_dyn_config.private_ev_cnt; i++) { in fconf_populate_sdei_dyn_config()
65 sdei_dyn_config.private_ev_nums[i] = PRIVATE_EVENT_NUM(i); in fconf_populate_sdei_dyn_config()
94 for (i = 0; i < sdei_dyn_config.shared_ev_cnt; i++) { in fconf_populate_sdei_dyn_config()
[all …]
A Dfconf_sec_intr_config.c13 #define G0_INTR_NUM(i) g0_intr_prop[3U * (i)] argument
14 #define G0_INTR_PRIORITY(i) g0_intr_prop[3U * (i) + 1] argument
15 #define G0_INTR_CONFIG(i) g0_intr_prop[3U * (i) + 2] argument
17 #define G1S_INTR_NUM(i) g1s_intr_prop[3U * (i)] argument
18 #define G1S_INTR_PRIORITY(i) g1s_intr_prop[3U * (i) + 1] argument
19 #define G1S_INTR_CONFIG(i) g1s_intr_prop[3U * (i) + 2] argument
103 for (uint32_t i = 0; i < g0_intr_count; i++) { in fconf_populate_sec_intr_config() local
108 sec_intr_property.intr_num = G0_INTR_NUM(i); in fconf_populate_sec_intr_config()
110 sec_intr_property.intr_cfg = G0_INTR_CONFIG(i); in fconf_populate_sec_intr_config()
116 for (uint32_t i = 0; i < g1s_intr_count; i++) { in fconf_populate_sec_intr_config() local
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/soc/
A Dsoc.c48 uint32_t i, j; in clk_gate_con_save() local
50 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_save()
53 j = i; in clk_gate_con_save()
54 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
61 uint32_t i, j; in clk_gate_con_restore() local
63 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_restore()
67 j = i; in clk_gate_con_restore()
68 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_restore()
75 uint32_t i; in clk_gate_con_disable() local
77 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_disable()
[all …]
/tf-a-ffa_el3_spmc/tools/cert_create/src/
A Dmain.c191 for (i = 0; i < KEY_SIZE_MAX_NUM; i++) { in check_cmd_params()
211 for (i = 0; i < num_certs; i++) { in check_cmd_params()
432 for (i = 0 ; i < num_keys ; i++) { in main()
472 for (i = 0 ; i < num_certs ; i++) { in main()
563 for (i = 0 ; i < num_certs ; i++) { in main()
573 for (i = 0 ; i < num_certs ; i++) { in main()
587 for (i = 0 ; i < num_keys ; i++) { in main()
597 for (i = 0; i < num_keys; i++) { in main()
608 for (i = 0; i < num_keys; i++) { in main()
616 for (i = 0; i < num_extensions; i++) { in main()
[all …]
/tf-a-ffa_el3_spmc/drivers/arm/gic/v3/
A Dgicv3_helpers.c149 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { in gicv3_spis_config_defaults()
168 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { in gicv3_spis_config_defaults()
173 for (i = MIN_ESPI_ID; i < num_eints; in gicv3_spis_config_defaults()
181 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { in gicv3_spis_config_defaults()
186 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { in gicv3_spis_config_defaults()
209 for (i = 0U; i < interrupt_props_num; i++) { in gicv3_secure_spis_config_props()
277 for (i = 0U; i < ppi_regs_num; ++i) { in gicv3_ppi_sgi_config_defaults()
285 for (i = 0U; i < ppi_regs_num; ++i) { in gicv3_ppi_sgi_config_defaults()
292 for (i = 0U; i < regs_num; ++i) { in gicv3_ppi_sgi_config_defaults()
299 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { in gicv3_ppi_sgi_config_defaults()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/dram/
A Ddfs.c277 for (i = 0; i < cnt; i++) { in get_rdlat_adj()
302 for (i = 0; i < cnt; i++) { in get_wrlat_adj()
997 for (i = 0; i < ch_cnt; i++) { in gen_rk3399_enable_training()
1008 for (i = 0; i < ch_cnt; i++) { in gen_rk3399_disable_training()
1437 for (i = 0; i < 4; i++) { in gen_rk3399_phy_dll_bypass()
1450 for (i = 0; i < 3; i++) in gen_rk3399_phy_dll_bypass()
1460 for (i = 0; i < 4; i++) { in gen_rk3399_phy_dll_bypass()
1478 for (i = 0; i < 4; i++) { in gen_rk3399_phy_dll_bypass()
1747 for (i = 0; i < 2; i++) { in exit_low_power()
1785 for (i = 0; i < 2; i++) { in resume_low_power()
[all …]
A Ddram.c17 uint32_t os_reg2_val, i; in dram_init() local
25 for (i = 0; i < 2; i++) { in dram_init()
29 if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i))) in dram_init()
32 ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); in dram_init()
33 ch->col = SYS_REG_DEC_COL(os_reg2_val, i); in dram_init()
34 ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); in dram_init()
35 ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); in dram_init()
36 ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); in dram_init()
37 ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); in dram_init()
38 ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i); in dram_init()
[all …]
/tf-a-ffa_el3_spmc/plat/imx/common/
A Dimx7_clock.c11 unsigned int i; in imx7_clock_uart_init() local
13 for (i = 0; i < MXC_MAX_UART_NUM; i++) in imx7_clock_uart_init()
14 imx_clock_disable_uart(i); in imx7_clock_uart_init()
19 unsigned int i; in imx7_clock_wdog_init() local
21 for (i = 0; i < MXC_MAX_WDOG_NUM; i++) in imx7_clock_wdog_init()
22 imx_clock_disable_wdog(i); in imx7_clock_wdog_init()
/tf-a-ffa_el3_spmc/plat/qti/common/src/
A Dqti_syscall.c77 for (i = 0; i < ARRAY_SIZE(qti_secure_io_allowed_regs); i++) { in qti_is_secure_io_access_allowed()
93 int i; in qti_mem_assign_validate_param() local
108 for (i = 0; i < u_num_mappings; i++) { in qti_mem_assign_validate_param()
135 for (i = 0; i < src_vm_list_cnt; i++) { in qti_mem_assign_validate_param()
138 i, (unsigned int)source_vm_list[i]); in qti_mem_assign_validate_param()
142 for (i = 0; i < dst_vm_list_cnt; i++) { in qti_mem_assign_validate_param()
236 for (int i = 0; i < u_num_mappings; i++) { in qti_sip_mem_assign() local
243 for (int i = 0; i < dst_vm_list_cnt; i++) { in qti_sip_mem_assign() local
246 dest_vm_list[i].ctx = dest_vm_list_p[i].ctx; in qti_sip_mem_assign()
252 for (int i = 0; i < src_vm_list_cnt; i++) { in qti_sip_mem_assign() local
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rcar/qos/M3N/
A Dqos_init_m3n_v10.c150 uint32_t i; in qos_init_m3n_v10() local
152 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3n_v10()
153 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_m3n_v10()
154 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_m3n_v10()
156 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3n_v10()
157 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_m3n_v10()
158 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_m3n_v10()
161 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_m3n_v10()
167 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_m3n_v10()
168 io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]); in qos_init_m3n_v10()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rzg/qos/G2N/
A Dqos_init_g2n_v10.c148 uint32_t i; in qos_init_g2n_v10() local
150 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2n_v10()
151 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2n_v10()
152 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2n_v10()
154 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2n_v10()
155 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2n_v10()
156 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2n_v10()
159 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2n_v10()
163 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_g2n_v10()
164 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]); in qos_init_g2n_v10()
[all …]
/tf-a-ffa_el3_spmc/plat/arm/common/aarch64/
A Darm_sdei.c29 uint32_t i; in plat_sdei_setup() local
33 for (i = 0; i < FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_cnt); i++) { in plat_sdei_setup()
34 arm_sdei_private[i + 1] = (sdei_ev_map_t)SDEI_PRIVATE_EVENT( in plat_sdei_setup()
35 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_nums[i]), in plat_sdei_setup()
36 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_intrs[i]), in plat_sdei_setup()
37 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_flags[i])); in plat_sdei_setup()
40 for (i = 0; i < FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_cnt); i++) { in plat_sdei_setup()
41 arm_sdei_shared[i] = (sdei_ev_map_t)SDEI_SHARED_EVENT( \ in plat_sdei_setup()
42 FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_nums[i]), in plat_sdei_setup()
43 FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_intrs[i]), in plat_sdei_setup()
[all …]
/tf-a-ffa_el3_spmc/drivers/marvell/
A Dap807_clocks_init.c47 int i; in pll_set_freq() local
52 for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) { in pll_set_freq()
58 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
61 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
65 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
74 int i; in aro_to_pll() local
76 for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) { in aro_to_pll()
78 reg = mmio_read_32(AP807_CPU_ARO_CTRL(i)); in aro_to_pll()
80 mmio_write_32(AP807_CPU_ARO_CTRL(i), reg); in aro_to_pll()
85 reg = mmio_read_32(AP807_CPU_ARO_CTRL(i)); in aro_to_pll()
[all …]
/tf-a-ffa_el3_spmc/plat/arm/board/rdv1mc/
A Drdv1mc_security.c44 unsigned int i; in plat_arm_security_setup() local
48 for (i = 0; i < TZC400_COUNT; i++) { in plat_arm_security_setup()
49 arm_tzc400_setup(TZC400_BASE(i), tzc_regions); in plat_arm_security_setup()
55 for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) { in plat_arm_security_setup()
56 INFO("Configuring TrustZone Controller for Chip %u\n", i); in plat_arm_security_setup()
59 arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i) in plat_arm_security_setup()
60 + TZC400_BASE(j), tzc_regions_mc[i-1]); in plat_arm_security_setup()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/soc/
A Dsoc.c145 uint32_t i = 0; in clk_gate_con_save() local
147 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_save()
154 uint32_t i; in clk_gate_con_disable() local
156 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_disable()
162 uint32_t i; in clk_gate_con_restore() local
164 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_restore()
173 for (i = 0; i < CRU_CLKSELS_CON_CNT; i++) in clk_sel_con_save()
182 for (i = 0; i < CRU_CLKSELS_CON_CNT; i++) { in clk_sel_con_restore()
184 if ((i >= 7 && i <= 9) || in clk_sel_con_restore()
185 (i >= 17 && i <= 20) || in clk_sel_con_restore()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rcar/qos/H3/
A Dqos_init_h3n_v30.c170 uint32_t i; in qos_init_h3n_v30() local
172 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_h3n_v30()
173 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_h3n_v30()
174 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_h3n_v30()
176 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_h3n_v30()
177 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_h3n_v30()
178 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_h3n_v30()
181 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_h3n_v30()
187 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_h3n_v30()
188 io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]); in qos_init_h3n_v30()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rzg/qos/G2H/
A Dqos_init_g2h_v30.c159 uint32_t i; in qos_init_g2h_v30() local
161 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2h_v30()
162 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2h_v30()
163 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2h_v30()
165 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2h_v30()
166 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2h_v30()
167 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2h_v30()
170 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2h_v30()
174 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_g2h_v30()
175 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]); in qos_init_g2h_v30()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rzg/qos/G2M/
A Dqos_init_g2m_v11.c104 uint32_t i; in qos_init_g2m_v11() local
160 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2m_v11()
161 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2m_v11()
162 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2m_v11()
164 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2m_v11()
165 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2m_v11()
166 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2m_v11()
169 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2m_v11()
173 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_g2m_v11()
174 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]); in qos_init_g2m_v11()
[all …]
A Dqos_init_g2m_v30.c104 uint32_t i; in qos_init_g2m_v30() local
161 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2m_v30()
162 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2m_v30()
163 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2m_v30()
165 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2m_v30()
166 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2m_v30()
167 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2m_v30()
170 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2m_v30()
174 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_g2m_v30()
175 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]); in qos_init_g2m_v30()
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/tf-a-ffa_el3_spmc/drivers/renesas/rcar/qos/M3/
A Dqos_init_m3_v11.c163 uint32_t i; in qos_init_m3_v11() local
165 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3_v11()
166 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_m3_v11()
167 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_m3_v11()
169 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3_v11()
170 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_m3_v11()
171 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_m3_v11()
174 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_m3_v11()
178 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_m3_v11()
179 io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]); in qos_init_m3_v11()
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