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/tf-a-ffa_el3_spmc/drivers/arm/gic/v3/
A Dgicdv3_helpers.c44 GICD_SET_BIT(IGROUP, base, id); in gicd_set_igroupr()
49 GICD_CLR_BIT(IGROUP, base, id); in gicd_clr_igroupr()
63 GICD_SET_BIT(IGRPMOD, base, id); in gicd_set_igrpmodr()
68 GICD_CLR_BIT(IGRPMOD, base, id); in gicd_clr_igrpmodr()
77 GICD_WRITE_BIT(ICENABLE, base, id); in gicd_set_icenabler()
86 GICD_WRITE_BIT(ICPEND, base, id); in gicd_set_icpendr()
118 GICD_WRITE_BIT(ISPEND, base, id); in gicd_set_ispendr()
140 return GICD_READ(ICFG, base, id); in gicd_read_icfgr()
145 GICD_WRITE(ICFG, base, id, val); in gicd_write_icfgr()
238 return GICD_READ(NSAC, base, id); in gicd_read_nsacr()
[all …]
A Dgicrv3_helpers.c26 return GICR_READ(IPRIORITY, base, id); in gicr_read_ipriorityr()
31 GICR_WRITE(IPRIORITY, base, id, val); in gicr_write_ipriorityr()
49 return GICR_GET_BIT(IGROUP, base, id); in gicr_get_igroupr()
54 GICR_SET_BIT(IGROUP, base, id); in gicr_set_igroupr()
59 GICR_CLR_BIT(IGROUP, base, id); in gicr_clr_igroupr()
73 GICR_SET_BIT(IGRPMOD, base, id); in gicr_set_igrpmodr()
78 GICR_CLR_BIT(IGRPMOD, base, id); in gicr_clr_igrpmodr()
87 GICR_WRITE_BIT(ISENABLE, base, id); in gicr_set_isenabler()
96 GICR_WRITE_BIT(ICENABLE, base, id); in gicr_set_icenabler()
114 GICR_WRITE_BIT(ICPEND, base, id); in gicr_set_icpendr()
[all …]
A Dgicv3_private.h28 #define BIT_NUM(REG, id) \ argument
38 (((id) <= MAX_SPI_ID) ? \
43 (((id) <= MAX_SPI_ID) ? \
49 (((id) <= MAX_SPI_ID) ? \
58 #define GICD_OFFSET(REG, id) \ argument
91 BIT_NUM(REG, (id))) & 1U)
115 (((id) <= MAX_PPI_ID) ? \
149 BIT_NUM(REG, (id))) & 1U)
275 assert(id >= MIN_SPI_ID); in gicd_read_irouter()
280 unsigned int id, in gicd_write_irouter() argument
[all …]
/tf-a-ffa_el3_spmc/drivers/arm/gic/common/
A Dgic_common.c25 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr()
36 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler()
47 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler()
58 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr()
69 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr()
113 unsigned int n = id >> ICFGR_SHIFT; in gicd_read_icfgr()
124 unsigned int n = id >> NSACR_SHIFT; in gicd_read_nsacr()
138 unsigned int n = id >> IGROUPR_SHIFT; in gicd_write_igroupr()
171 unsigned int n = id >> ISPENDR_SHIFT; in gicd_write_ispendr()
226 unsigned int n = id >> ICFGR_SHIFT; in gicd_write_icfgr()
[all …]
A Dgic_common_private.h43 unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id);
51 unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id);
52 unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id);
77 void gicd_set_igroupr(uintptr_t base, unsigned int id);
78 void gicd_clr_igroupr(uintptr_t base, unsigned int id);
79 void gicd_set_isenabler(uintptr_t base, unsigned int id);
80 void gicd_set_icenabler(uintptr_t base, unsigned int id);
81 void gicd_set_ispendr(uintptr_t base, unsigned int id);
82 void gicd_set_icpendr(uintptr_t base, unsigned int id);
84 void gicd_set_isactiver(uintptr_t base, unsigned int id);
[all …]
/tf-a-ffa_el3_spmc/drivers/arm/gic/v2/
A Dgicdv2_helpers.c23 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr()
34 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler()
45 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler()
56 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr()
67 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr()
111 unsigned int n = id >> ICFGR_SHIFT; in gicd_read_icfgr()
122 unsigned int n = id >> NSACR_SHIFT; in gicd_read_nsacr()
136 unsigned int n = id >> IGROUPR_SHIFT; in gicd_write_igroupr()
169 unsigned int n = id >> ISPENDR_SHIFT; in gicd_write_ispendr()
224 unsigned int n = id >> ICFGR_SHIFT; in gicd_write_icfgr()
[all …]
A Dgicv2_main.c211 unsigned int id; in gicv2_get_pending_interrupt_id() local
222 if (id == PENDING_G1_INTID) in gicv2_get_pending_interrupt_id()
225 return id; in gicv2_get_pending_interrupt_id()
336 assert(id <= MAX_SPI_ID); in gicv2_get_interrupt_active()
348 assert(id <= MAX_SPI_ID); in gicv2_enable_interrupt()
365 assert(id <= MAX_SPI_ID); in gicv2_disable_interrupt()
383 assert(id <= MAX_SPI_ID); in gicv2_set_interrupt_priority()
396 assert(id <= MAX_SPI_ID); in gicv2_set_interrupt_type()
463 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID)); in gicv2_set_spi_routing()
495 assert(id >= MIN_PPI_ID); in gicv2_clear_interrupt_pending()
[all …]
/tf-a-ffa_el3_spmc/plat/common/
A Dplat_gicv2.c45 unsigned int id; in plat_ic_get_pending_interrupt_id() local
51 return id; in plat_ic_get_pending_interrupt_id()
67 unsigned int id; in plat_ic_get_pending_interrupt_type() local
72 if (id < PENDING_G1_INTID) { in plat_ic_get_pending_interrupt_type()
122 gicv2_end_of_interrupt(id); in plat_ic_end_of_interrupt()
160 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); in plat_ic_is_spi()
165 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); in plat_ic_is_ppi()
170 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); in plat_ic_is_sgi()
241 int id; in plat_ic_raise_el3_sgi() local
245 assert(id >= 0); in plat_ic_raise_el3_sgi()
[all …]
A Dplat_gicv3.c131 gicv3_end_of_interrupt(id); in plat_ic_end_of_interrupt()
189 int plat_ic_is_spi(unsigned int id) in plat_ic_is_spi() argument
191 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); in plat_ic_is_spi()
194 int plat_ic_is_ppi(unsigned int id) in plat_ic_is_ppi() argument
196 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); in plat_ic_is_ppi()
199 int plat_ic_is_sgi(unsigned int id) in plat_ic_is_sgi() argument
201 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); in plat_ic_is_sgi()
272 assert(id >= MIN_PPI_ID); in plat_ic_set_interrupt_pending()
279 assert(id >= MIN_PPI_ID); in plat_ic_clear_interrupt_pending()
293 INTR_ID_UNAVAILABLE : id; in plat_ic_get_interrupt_id()
[all …]
/tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/aarch64/
A Dzynqmp_common.c64 .id = 0x10,
68 .id = 0x10,
73 .id = 0x11,
77 .id = 0x11,
82 .id = 0x20,
87 .id = 0x20,
93 .id = 0x20,
98 .id = 0x21,
103 .id = 0x21,
245 if (zynqmp_devices[i].id == id && in zynqmp_get_silicon_idcode_name()
[all …]
/tf-a-ffa_el3_spmc/include/drivers/st/
A Dstm32mp1_clk.h31 void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure);
32 void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure);
34 static inline void stm32mp1_clk_enable_non_secure(unsigned long id) in stm32mp1_clk_enable_non_secure() argument
36 __stm32mp1_clk_enable(id, false); in stm32mp1_clk_enable_non_secure()
39 static inline void stm32mp1_clk_enable_secure(unsigned long id) in stm32mp1_clk_enable_secure() argument
41 __stm32mp1_clk_enable(id, true); in stm32mp1_clk_enable_secure()
46 __stm32mp1_clk_disable(id, false); in stm32mp1_clk_disable_non_secure()
49 static inline void stm32mp1_clk_disable_secure(unsigned long id) in stm32mp1_clk_disable_secure() argument
51 __stm32mp1_clk_disable(id, true); in stm32mp1_clk_disable_secure()
54 unsigned int stm32mp1_clk_get_refcount(unsigned long id);
[all …]
/tf-a-ffa_el3_spmc/plat/st/stm32mp1/
A Dstm32mp1_shared_resources.c74 return shres2str_id_tbl[id]; in shres2str_id()
153 shres2str_id(id), in register_periph()
178 switch (id) { in register_periph()
238 enum stm32mp_shres id; in register_periph_iomem() local
248 id = STM32MP1_SHRES_I2C4; in register_periph_iomem()
251 id = STM32MP1_SHRES_I2C6; in register_periph_iomem()
257 id = STM32MP1_SHRES_RNG1; in register_periph_iomem()
260 id = STM32MP1_SHRES_RTC; in register_periph_iomem()
480 switch (id) { in mckprot_protects_periph()
570 unsigned int id; in print_shared_resources_state() local
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/soc/
A Dsoc.h71 #define CRU_AUTOCS_CON0(id) (0x400 + (id) * 8) argument
72 #define CRU_AUTOCS_CON1(id) (0x404 + (id) * 8) argument
92 #define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4) argument
96 #define PLL_MODE_SHIFT(id) ((id) == CPLL_ID ? \ argument
98 ((id) == DPLL_ID ? 4 : 2 * (id)))
99 #define PLL_MODE_MSK(id) (0x3 << PLL_MODE_SHIFT(id)) argument
/tf-a-ffa_el3_spmc/fdts/
A Dcot_descriptors.dtsi188 image-id = <HW_CONFIG_ID>;
206 image-id = <BL31_IMAGE_ID>;
255 image-id = <SP_PKG1_ID>;
261 image-id = <SP_PKG2_ID>;
267 image-id = <SP_PKG3_ID>;
273 image-id = <SP_PKG4_ID>;
279 image-id = <SP_PKG5_ID>;
285 image-id = <SP_PKG6_ID>;
291 image-id = <SP_PKG7_ID>;
297 image-id = <SP_PKG8_ID>;
[all …]
/tf-a-ffa_el3_spmc/tools/cert_create/src/tbbr/
A Dtbb_key.c16 .id = ROT_KEY,
22 .id = TRUSTED_WORLD_KEY,
28 .id = NON_TRUSTED_WORLD_KEY,
34 .id = SCP_FW_CONTENT_CERT_KEY,
40 .id = SOC_FW_CONTENT_CERT_KEY,
46 .id = TRUSTED_OS_FW_CONTENT_CERT_KEY,
52 .id = NON_TRUSTED_FW_CONTENT_CERT_KEY,
A Dtbb_cert.c20 .id = TRUSTED_BOOT_FW_CERT,
37 .id = TRUSTED_KEY_CERT,
52 .id = SCP_FW_KEY_CERT,
66 .id = SCP_FW_CONTENT_CERT,
80 .id = SOC_FW_KEY_CERT,
94 .id = SOC_FW_CONTENT_CERT,
109 .id = TRUSTED_OS_FW_KEY_CERT,
123 .id = TRUSTED_OS_FW_CONTENT_CERT,
140 .id = NON_TRUSTED_FW_KEY_CERT,
154 .id = NON_TRUSTED_FW_CONTENT_CERT,
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/sspm/
A Dsspm.c61 static int sspm_ipi_check_ack(uint32_t id) in sspm_ipi_check_ack() argument
65 if (id == IPI_ID_PLATFORM) { in sspm_ipi_check_ack()
68 } else if (id == IPI_ID_SUSPEND) { in sspm_ipi_check_ack()
72 ERROR("%s: id = %d\n", __func__, id); in sspm_ipi_check_ack()
79 int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data) in sspm_ipi_send_non_blocking() argument
83 ret = sspm_ipi_check_ack(id); in sspm_ipi_send_non_blocking()
87 if (id == IPI_ID_PLATFORM) { in sspm_ipi_send_non_blocking()
93 } else if (id == IPI_ID_SUSPEND) { in sspm_ipi_send_non_blocking()
109 ret = sspm_ipi_check_ack(id); in sspm_ipi_recv_non_blocking()
111 if (id == IPI_ID_PLATFORM) { in sspm_ipi_recv_non_blocking()
[all …]
/tf-a-ffa_el3_spmc/bl32/tsp/
A Dtsp_interrupt.c78 uint32_t linear_id = plat_my_core_pos(), id; in tsp_common_int_handler() local
90 id = plat_ic_get_pending_interrupt_id(); in tsp_common_int_handler()
93 if (id != TSP_IRQ_SEC_PHY_TIMER) in tsp_common_int_handler()
100 INFO("Unexpected interrupt id %u\n", id); in tsp_common_int_handler()
110 id = plat_ic_acknowledge_interrupt(); in tsp_common_int_handler()
111 assert(id == TSP_IRQ_SEC_PHY_TIMER); in tsp_common_int_handler()
113 plat_ic_end_of_interrupt(id); in tsp_common_int_handler()
120 read_mpidr(), id); in tsp_common_int_handler()
/tf-a-ffa_el3_spmc/include/lib/fconf/
A Dfconf_tbbr_getter.h15 #define tbbr__cot_getter(id) __extension__ ({ \ argument
16 assert((id) < cot_desc_size); \
17 cot_desc_ptr[id]; \
20 #define tbbr__dyn_config_getter(id) tbbr_dyn_config.id argument
/tf-a-ffa_el3_spmc/plat/ti/k3/common/drivers/ti_sci/
A Dti_sci.h52 int ti_sci_device_get(uint32_t id);
53 int ti_sci_device_get_exclusive(uint32_t id);
54 int ti_sci_device_idle(uint32_t id);
55 int ti_sci_device_idle_exclusive(uint32_t id);
56 int ti_sci_device_put(uint32_t id);
57 int ti_sci_device_put_no_wait(uint32_t id);
58 int ti_sci_device_is_valid(uint32_t id);
59 int ti_sci_device_get_clcnt(uint32_t id, uint32_t *count);
60 int ti_sci_device_is_idle(uint32_t id, bool *r_state);
63 int ti_sci_device_is_trans(uint32_t id, bool *curr_state);
[all …]
/tf-a-ffa_el3_spmc/include/drivers/arm/
A Dgicv3.h54 #define IS_SGI_PPI(id) (((id) <= MAX_PPI_ID) || \ argument
55 (((id) >= MIN_EPPI_ID) && \
56 ((id) <= MAX_EPPI_ID)))
59 #define IS_SPI(id) ((((id) >= MIN_SPI_ID) && \ argument
60 ((id) <= MAX_SPI_ID)) || \
61 (((id) >= MIN_ESPI_ID) && \
62 ((id) <= MAX_ESPI_ID)))
72 #define IS_SGI_PPI(id) ((id) <= MAX_PPI_ID) argument
75 #define IS_SPI(id) (((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID)) argument
317 return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT); in gicv3_is_intr_id_special_identifier()
[all …]
/tf-a-ffa_el3_spmc/plat/arm/board/rde1edge/fdts/
A Drde1edge_nt_fw_config.dts13 * Place holder for system-id node with default values. The
14 * value of platform-id and config-id will be set to the
17 system-id {
18 platform-id = <0x0>;
19 config-id = <0x0>;
/tf-a-ffa_el3_spmc/plat/arm/board/sgi575/fdts/
A Dsgi575_nt_fw_config.dts13 * Place holder for system-id node with default values. The
14 * value of platform-id and config-id will be set to the
17 system-id {
18 platform-id = <0x0>;
19 config-id = <0x0>;
/tf-a-ffa_el3_spmc/plat/imx/common/
A Dimx_clock.c16 void imx_clock_target_set(unsigned int id, uint32_t val) in imx_clock_target_set() argument
21 if (id > CCM_ROOT_CTRL_NUM) in imx_clock_target_set()
24 addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root; in imx_clock_target_set()
28 void imx_clock_target_clr(unsigned int id, uint32_t val) in imx_clock_target_clr() argument
33 if (id > CCM_ROOT_CTRL_NUM) in imx_clock_target_clr()
36 addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root_clr; in imx_clock_target_clr()
40 void imx_clock_gate_enable(unsigned int id, bool enable) in imx_clock_gate_enable() argument
45 if (id > CCM_CLK_GATE_CTRL_NUM) in imx_clock_gate_enable()
50 addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_set; in imx_clock_gate_enable()
52 addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_clr; in imx_clock_gate_enable()
/tf-a-ffa_el3_spmc/plat/arm/board/rdn1edge/fdts/
A Drdn1edge_nt_fw_config.dts13 * Place holder for system-id node with default values. The
14 * value of platform-id and config-id will be set to the
17 system-id {
18 platform-id = <0x0>;
19 config-id = <0x0>;

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