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/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/mcdi/
A Dmt_lp_irqremain.c68 uint32_t idx; in mt_lp_irqremain_init() local
73 idx = remain_irqs.count; in mt_lp_irqremain_init()
80 idx = remain_irqs.count; in mt_lp_irqremain_init()
87 idx = remain_irqs.count; in mt_lp_irqremain_init()
94 idx = remain_irqs.count; in mt_lp_irqremain_init()
101 idx = remain_irqs.count; in mt_lp_irqremain_init()
108 idx = remain_irqs.count; in mt_lp_irqremain_init()
115 idx = remain_irqs.count; in mt_lp_irqremain_init()
122 idx = remain_irqs.count; in mt_lp_irqremain_init()
129 idx = remain_irqs.count; in mt_lp_irqremain_init()
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/tf-a-ffa_el3_spmc/include/lib/extensions/
A Damu_private.h12 uint64_t amu_group0_cnt_read_internal(unsigned int idx);
13 void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val);
15 uint64_t amu_group1_cnt_read_internal(unsigned int idx);
16 void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val);
17 void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val);
20 uint64_t amu_group0_voffset_read_internal(unsigned int idx);
21 void amu_group0_voffset_write_internal(unsigned int idx, uint64_t val);
23 uint64_t amu_group1_voffset_read_internal(unsigned int idx);
24 void amu_group1_voffset_write_internal(unsigned int idx, uint64_t val);
A Dras_arch.h200 return mmio_read_64(base + ERR_FR(idx)); in ser_get_feature()
205 return mmio_read_64(base + ERR_CTLR(idx)); in ser_get_control()
210 return mmio_read_64(base + ERR_STATUS(idx)); in ser_get_status()
224 static inline void ser_set_status(uintptr_t base, unsigned int idx, in ser_set_status() argument
227 mmio_write_64(base + ERR_STATUS(idx), status); in ser_set_status()
232 return mmio_read_64(base + ERR_ADDR(idx)); in ser_get_addr()
237 return mmio_read_64(base + ERR_MISC0(idx)); in ser_get_misc0()
242 return mmio_read_64(base + ERR_MISC1(idx)); in ser_get_misc1()
249 static inline void ser_sys_select_record(unsigned int idx) in ser_sys_select_record() argument
254 assert(idx < max_idx); in ser_sys_select_record()
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A Damu.h91 uint64_t amu_group0_cnt_read(unsigned int idx);
92 void amu_group0_cnt_write(unsigned int idx, uint64_t val);
95 uint64_t amu_group0_voffset_read(unsigned int idx);
96 void amu_group0_voffset_write(unsigned int idx, uint64_t val);
103 uint64_t amu_group1_cnt_read(unsigned int idx);
104 void amu_group1_cnt_write(unsigned int idx, uint64_t val);
105 void amu_group1_set_evtype(unsigned int idx, unsigned int val);
108 uint64_t amu_group1_voffset_read(unsigned int idx);
109 void amu_group1_voffset_write(unsigned int idx, uint64_t val);
/tf-a-ffa_el3_spmc/lib/extensions/amu/aarch64/
A Damu.c136 assert(idx < AMU_GROUP0_NR_COUNTERS); in amu_group0_cnt_read()
145 assert(idx < AMU_GROUP0_NR_COUNTERS); in amu_group0_cnt_write()
160 assert(idx < AMU_GROUP0_NR_COUNTERS); in amu_group0_voffset_read()
161 assert(idx != 1U); in amu_group0_voffset_read()
175 assert(idx < AMU_GROUP0_NR_COUNTERS); in amu_group0_voffset_write()
176 assert(idx != 1U); in amu_group0_voffset_write()
188 assert(idx < AMU_GROUP1_NR_COUNTERS); in amu_group1_cnt_read()
198 assert(idx < AMU_GROUP1_NR_COUNTERS); in amu_group1_cnt_write()
213 assert(idx < AMU_GROUP1_NR_COUNTERS); in amu_group1_voffset_read()
215 (1ULL << idx)) != 0ULL); in amu_group1_voffset_read()
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/tf-a-ffa_el3_spmc/bl31/
A Dehf.c34 #define PRI_BIT(idx) (((ehf_pri_bits_t) 1u) << (idx)) argument
40 #define IDX_TO_PRI(idx) \ argument
44 #define IS_IDX_VALID(idx) \ argument
56 unsigned int idx; in pri_to_idx() local
60 assert(IS_IDX_VALID(idx)); in pri_to_idx()
62 return idx; in pri_to_idx()
123 idx = pri_to_idx(priority); in ehf_activate_priority()
430 idx = pri_to_idx(pri); in ehf_el3_interrupt_handler()
439 IDX_TO_PRI(idx)); in ehf_el3_interrupt_handler()
496 unsigned int idx; in ehf_register_priority_handler() local
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/tf-a-ffa_el3_spmc/plat/marvell/armada/common/
A Dmarvell_gicv2.c35 #define A7K8K_ODMI_PMU_IRQ(idx) ((2 + idx) << 12) argument
37 #define A7K8K_ODMI_PMU_GIC_IRQ(idx) (130 + idx) argument
79 unsigned int idx = plat_my_core_pos(); in a7k8k_pmu_interrupt_handler() local
98 mmio_write_32(A7K8K_ODMIN_SET_REG, A7K8K_ODMI_PMU_IRQ(idx)); in a7k8k_pmu_interrupt_handler()
107 unsigned int idx; in mvebu_pmu_interrupt_enable() local
117 for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) in mvebu_pmu_interrupt_enable()
118 gicv2_interrupt_set_cfg(A7K8K_ODMI_PMU_GIC_IRQ(idx), in mvebu_pmu_interrupt_enable()
/tf-a-ffa_el3_spmc/lib/extensions/amu/aarch32/
A Damu.c116 uint64_t amu_group0_cnt_read(unsigned int idx) in amu_group0_cnt_read() argument
119 assert(idx < AMU_GROUP0_NR_COUNTERS); in amu_group0_cnt_read()
121 return amu_group0_cnt_read_internal(idx); in amu_group0_cnt_read()
128 assert(idx < AMU_GROUP0_NR_COUNTERS); in amu_group0_cnt_write()
130 amu_group0_cnt_write_internal(idx, val); in amu_group0_cnt_write()
140 assert(idx < AMU_GROUP1_NR_COUNTERS); in amu_group1_cnt_read()
142 return amu_group1_cnt_read_internal(idx); in amu_group1_cnt_read()
150 assert(idx < AMU_GROUP1_NR_COUNTERS); in amu_group1_cnt_write()
152 amu_group1_cnt_write_internal(idx, val); in amu_group1_cnt_write()
164 assert(idx < AMU_GROUP1_NR_COUNTERS); in amu_group1_set_evtype()
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/tf-a-ffa_el3_spmc/tools/cert_create/src/
A Dcmd_opt.c43 const char *cmd_opt_get_name(int idx) in cmd_opt_get_name() argument
45 if (idx >= num_reg_opt) { in cmd_opt_get_name()
49 return long_opt[idx].name; in cmd_opt_get_name()
52 const char *cmd_opt_get_help_msg(int idx) in cmd_opt_get_help_msg() argument
54 if (idx >= num_reg_opt) { in cmd_opt_get_help_msg()
58 return help_msg[idx]; in cmd_opt_get_help_msg()
/tf-a-ffa_el3_spmc/tools/encrypt_fw/src/
A Dcmd_opt.c43 const char *cmd_opt_get_name(int idx) in cmd_opt_get_name() argument
45 if (idx >= num_reg_opt) { in cmd_opt_get_name()
49 return long_opt[idx].name; in cmd_opt_get_name()
52 const char *cmd_opt_get_help_msg(int idx) in cmd_opt_get_help_msg() argument
54 if (idx >= num_reg_opt) { in cmd_opt_get_help_msg()
58 return help_msg[idx]; in cmd_opt_get_help_msg()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_pmic_wrap.c102 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
154 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_get_cmd()
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/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/spm/
A Dmt_spm_pmic_wrap.c102 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
154 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_get_cmd()
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/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/mcdi/
A Dmt_lp_irqremain.c58 uint32_t idx; in mt_lp_irqremain_init() local
63 idx = remain_irqs.count; in mt_lp_irqremain_init()
64 remain_irqs.irqs[idx] = KEYPAD_IRQ_ID; in mt_lp_irqremain_init()
65 remain_irqs.wakeupsrc_cat[idx] = 0; in mt_lp_irqremain_init()
66 remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC; in mt_lp_irqremain_init()
/tf-a-ffa_el3_spmc/plat/mediatek/common/lpm/
A Dmt_lp_rm.c39 int mt_lp_rm_reset_constraint(int idx, unsigned int cpuid, int stateid) in mt_lp_rm_reset_constraint() argument
43 if ((plat_mt_rm.plat_rm == NULL) || (idx < 0) || in mt_lp_rm_reset_constraint()
44 (idx >= plat_mt_rm.count)) { in mt_lp_rm_reset_constraint()
48 rc = plat_mt_rm.plat_rm->consts[idx]; in mt_lp_rm_reset_constraint()
57 int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid, in mt_lp_rm_find_and_run_constraint() argument
64 if ((rm == NULL) || (idx < 0) || (idx >= plat_mt_rm.count)) { in mt_lp_rm_find_and_run_constraint()
76 for (i = idx, rc = (rm->consts + idx); *rc != NULL; i++, rc++) { in mt_lp_rm_find_and_run_constraint()
/tf-a-ffa_el3_spmc/plat/st/common/
A Dbl2_io_storage.c342 uint8_t idx; in boot_mmc() local
386 idx = IMG_IDX_BL33; in boot_mmc()
413 for (idx = 0U; idx < IMG_IDX_NUM; idx++) { in boot_mmc()
445 uint8_t idx; in boot_spi_nor() local
462 idx = IMG_IDX_BL33; in boot_spi_nor()
478 idx = IMG_IDX_OPTEE_CORE; in boot_spi_nor()
490 uint8_t idx; in boot_fmc2_nand() local
507 idx = IMG_IDX_BL33; in boot_fmc2_nand()
523 idx = IMG_IDX_OPTEE_CORE; in boot_fmc2_nand()
535 uint8_t idx; in boot_spi_nand() local
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/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/spm/
A Dspm_pmic_wrap.c117 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
134 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
147 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
150 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
155 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
156 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
165 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_get_cmd()
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/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/
A Diommu.c316 ARM_SMMU_GR0_SMR(idx)), reg); in arm_smmu_smr_cfg()
329 ARM_SMMU_GR0_S2CR(idx)), reg); in arm_smmu_s2cr_cfg()
404 uint32_t idx; in arm_smmu_create_identity_map() local
441 for (idx = 0; idx < smmu->streams; idx++) { in arm_smmu_create_identity_map()
448 arm_smmu_s2cr_cfg(smmu, idx); in arm_smmu_create_identity_map()
451 smmu->smr[idx].mask = smmu->stream_ids_mask[idx]; in arm_smmu_create_identity_map()
452 smmu->smr[idx].id = smmu->stream_ids[idx]; in arm_smmu_create_identity_map()
453 smmu->smr[idx].valid = 1; in arm_smmu_create_identity_map()
454 arm_smmu_smr_cfg(smmu, idx); in arm_smmu_create_identity_map()
461 reg = smmu->cfg[idx].cbar; in arm_smmu_create_identity_map()
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/tf-a-ffa_el3_spmc/drivers/auth/
A Dimg_parser_mod.c69 unsigned int idx; in img_parser_check_integrity() local
80 idx = parser_lib_indices[img_type]; in img_parser_check_integrity()
81 assert(idx != INVALID_IDX); in img_parser_check_integrity()
84 return parser_lib_descs[idx].check_integrity(img_ptr, img_len); in img_parser_check_integrity()
103 unsigned int idx; in img_parser_get_auth_param() local
120 idx = parser_lib_indices[img_type]; in img_parser_get_auth_param()
121 assert(idx != INVALID_IDX); in img_parser_get_auth_param()
124 return parser_lib_descs[idx].get_auth_param(type_desc, img_ptr, img_len, in img_parser_get_auth_param()
/tf-a-ffa_el3_spmc/services/std_svc/sdei/
A Dsdei_event.c27 long int idx; in get_event_entry() local
35 idx = MAP_OFF(map, mapping); in get_event_entry()
45 return &cpu_priv_base[idx]; in get_event_entry()
48 idx = MAP_OFF(map, mapping); in get_event_entry()
50 return &sdei_shared_event_table[idx]; in get_event_entry()
/tf-a-ffa_el3_spmc/drivers/st/iwdg/
A Dstm32_iwdg.c90 uint32_t idx; in stm32_iwdg_init() local
94 idx = stm32_iwdg_get_instance(dt_info.base); in stm32_iwdg_init()
95 iwdg = &stm32_iwdg[idx]; in stm32_iwdg_init()
111 hw_init = stm32_iwdg_get_otp_config(idx); in stm32_iwdg_init()
116 idx + 1U); in stm32_iwdg_init()
136 VERBOSE("IWDG%u found, %ssecure\n", idx + 1U, in stm32_iwdg_init()
147 if (stm32_iwdg_shadow_update(idx, iwdg->flags) != BSEC_OK) { in stm32_iwdg_init()
/tf-a-ffa_el3_spmc/lib/psci/
A Dpsci_common.c895 unsigned int idx; in psci_print_power_domain_map() local
907 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count); in psci_print_power_domain_map()
908 idx++) { in psci_print_power_domain_map()
913 psci_non_cpu_pd_nodes[idx].level, in psci_print_power_domain_map()
919 for (idx = 0; idx < psci_plat_core_count; idx++) { in psci_print_power_domain_map()
925 psci_cpu_pd_nodes[idx].parent_node, in psci_print_power_domain_map()
941 unsigned int idx, n_valid = 0U; in psci_secondaries_brought_up() local
943 for (idx = 0U; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) { in psci_secondaries_brought_up()
993 unsigned int idx, this_cpu_idx; in psci_stop_other_cores() local
998 for (idx = 0U; idx < psci_plat_core_count; idx++) { in psci_stop_other_cores()
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/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/spm/constraints/
A Dmt_spm_rc_bus26m.c110 unsigned int idx; in do_irqs_delivery() local
121 for (idx = 0U; idx < irqs->count; ++idx) { in do_irqs_delivery()
122 if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) || in do_irqs_delivery()
123 ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) { in do_irqs_delivery()
124 if ((irqs->wakeupsrc_cat[idx] & in do_irqs_delivery()
126 mt_spm_irq_remain_dump(irqs, idx, wakeup); in do_irqs_delivery()
129 mt_irq_set_pending(irqs->irqs[idx]); in do_irqs_delivery()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/spm/constraints/
A Dmt_spm_rc_bus26m.c120 unsigned int idx; in do_irqs_delivery() local
131 for (idx = 0U; idx < irqs->count; ++idx) { in do_irqs_delivery()
132 if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) || in do_irqs_delivery()
133 ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) { in do_irqs_delivery()
134 if ((irqs->wakeupsrc_cat[idx] & in do_irqs_delivery()
136 mt_spm_irq_remain_dump(irqs, idx, wakeup); in do_irqs_delivery()
139 mt_irq_set_pending(irqs->irqs[idx]); in do_irqs_delivery()
/tf-a-ffa_el3_spmc/include/plat/arm/common/
A Dfconf_ethosn_getter.h15 #define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \ argument
16 assert(idx < ethosn_config.num_cores); \
17 ethosn_config.core_addr[idx]; \
/tf-a-ffa_el3_spmc/drivers/marvell/
A Dio_win.c186 int win_id, idx; in iow_save_win_range() local
189 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { in iow_save_win_range()
190 buffer[idx++] = mmio_read_32(IO_WIN_CR_OFFSET(ap_id, win_id)); in iow_save_win_range()
191 buffer[idx++] = mmio_read_32(IO_WIN_ALR_OFFSET(ap_id, win_id)); in iow_save_win_range()
192 buffer[idx++] = mmio_read_32(IO_WIN_AHR_OFFSET(ap_id, win_id)); in iow_save_win_range()
194 buffer[idx] = mmio_read_32(MVEBU_IO_WIN_BASE(ap_id) + in iow_save_win_range()
201 int win_id, idx; in iow_restore_win_range() local
205 mmio_write_32(IO_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]); in iow_restore_win_range()
206 mmio_write_32(IO_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]); in iow_restore_win_range()
207 mmio_write_32(IO_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]); in iow_restore_win_range()
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