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/tf-a-ffa_el3_spmc/lib/psci/
A Dpsci_setup.c98 int j; in psci_update_pwrlvl_limits() local
106 for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { in psci_update_pwrlvl_limits()
107 if (temp_index[j] != nodes_idx[j]) { in psci_update_pwrlvl_limits()
108 nodes_idx[j] = temp_index[j]; in psci_update_pwrlvl_limits()
112 psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++; in psci_update_pwrlvl_limits()
155 for (j = node_index; in populate_power_domain_tree()
156 j < (node_index + num_children); j++) in populate_power_domain_tree()
157 psci_init_pwr_domain_node((uint16_t)j, in populate_power_domain_tree()
161 node_index = j; in populate_power_domain_tree()
175 assert(j <= PLATFORM_CORE_COUNT); in populate_power_domain_tree()
[all …]
/tf-a-ffa_el3_spmc/plat/xilinx/common/pm_service/
A Dpm_ipi.c141 size_t j; in pm_ipi_buff_read() local
160 for (j = 0; j < PAYLOAD_ARG_CNT; j++) in pm_ipi_buff_read()
161 response_payload[j] = mmio_read_32(buffer_base + in pm_ipi_buff_read()
162 (j * PAYLOAD_ARG_SIZE)); in pm_ipi_buff_read()
185 size_t j; in pm_ipi_buff_read_callb() local
200 for (j = 0; j < PAYLOAD_ARG_CNT; j++) in pm_ipi_buff_read_callb()
202 (j * PAYLOAD_ARG_SIZE)); in pm_ipi_buff_read_callb()
280 j = 0x80U; in calculate_crc()
281 while (j != 0U) { in calculate_crc()
284 if (0U != (c & j)) in calculate_crc()
[all …]
/tf-a-ffa_el3_spmc/plat/arm/board/rdv1mc/
A Drdv1mc_security.c53 unsigned int j; in plat_arm_security_setup() local
58 for (j = 0; j < TZC400_COUNT; j++) { in plat_arm_security_setup()
60 + TZC400_BASE(j), tzc_regions_mc[i-1]); in plat_arm_security_setup()
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/soc/
A Dsoc.c48 uint32_t i, j; in clk_gate_con_save() local
53 j = i; in clk_gate_con_save()
54 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
55 clkgt_save[j] = in clk_gate_con_save()
61 uint32_t i, j; in clk_gate_con_restore() local
67 j = i; in clk_gate_con_restore()
68 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_restore()
70 WITH_16BITS_WMSK(clkgt_save[j])); in clk_gate_con_restore()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/crypt/
A Dcrypt.c59 uint32_t j = 0; in crypt_set_hdcp_key_ex() local
88 for (j = 0; j < 4; j++) { in crypt_set_hdcp_key_ex()
90 crypt_write32(REG_P69, 0x34 + 4 * i + j); in crypt_set_hdcp_key_ex()
91 crypt_write32(REG_P70, record[j]); in crypt_set_hdcp_key_ex()
/tf-a-ffa_el3_spmc/tools/encrypt_fw/src/
A Dencrypt.c31 int bytes, enc_len = 0, i, j, ret = 0; in gcm_encrypt() local
41 for (i = 0, j = 0; i < KEY_SIZE; i++, j += 2) { in gcm_encrypt()
42 if (sscanf(&key_string[j], "%02hhx", &key[i]) != 1) { in gcm_encrypt()
53 for (i = 0, j = 0; i < IV_SIZE; i++, j += 2) { in gcm_encrypt()
54 if (sscanf(&nonce_string[j], "%02hhx", &iv[i]) != 1) { in gcm_encrypt()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/
A Dplat_ras.c105 for (uint32_t j = 0; j < num_idx; j++) { in tegra194_ras_enable() local
120 assert(aux_data[j].err_ctrl != NULL); in tegra194_ras_enable()
127 ser_sys_select_record(idx_start + j); in tegra194_ras_enable()
130 uncorr_errs = aux_data[j].err_ctrl(); in tegra194_ras_enable()
150 idx_start + j, err_fr, err_ctrl); in tegra194_ras_enable()
215 uint32_t j; in tegra194_ras_corrected_err_clear() local
217 j = (i == prev.rec.last_node && prev.value != 0UL) ? in tegra194_ras_corrected_err_clear()
220 for (; j < num_idx; j++) { in tegra194_ras_corrected_err_clear()
223 uint32_t err_idx = idx_start + j; in tegra194_ras_corrected_err_clear()
240 prev.rec.last_idx = j; in tegra194_ras_corrected_err_clear()
/tf-a-ffa_el3_spmc/lib/zlib/
A Dzutil.c165 uInt j; local
167 for (j = 0; j < len; j++) {
168 if (s1[j] != s2[j]) return 2*(s1[j] > s2[j])-1;
/tf-a-ffa_el3_spmc/plat/qemu/common/
A Dqemu_spm.c64 unsigned int i, j; in qemu_initialize_mp_info() local
68 for (j = 0; j < PLATFORM_MAX_CPUS_PER_CLUSTER; j++) { in qemu_initialize_mp_info()
69 tmp->mpidr = (0x80000000 | (i << MPIDR_AFF1_SHIFT)) + j; in qemu_initialize_mp_info()
/tf-a-ffa_el3_spmc/drivers/nxp/flexspi/nor/
A Dfspi.c282 uint32_t i = 0U, j = 0U, x_rem = 0U; in xspi_ip_read() local
349 for (j = 0U; j < x_size_wm; j += 4U) { in xspi_ip_read()
351 data = fspi_readl(FSPI_RFDR + j); in xspi_ip_read()
372 j = 0U; in xspi_ip_read()
408 uint32_t i = 0U, j = 0U; in xspi_ip_write() local
443 for (j = 0U; j < x_size_wm; j += 4U) { in xspi_ip_write()
463 j = 0U; in xspi_ip_write()
503 uint32_t i, j = 0U; in xspi_write() local
520 j = 0U; in xspi_write()
524 j = ui_len / F_PAGE_256; in xspi_write()
[all …]
/tf-a-ffa_el3_spmc/drivers/nxp/ddr/nxp-ddr/
A Dregs.c938 int j; in cal_ddr_addr_dec() local
1031 for (j = 0; j < 18; j++) { in cal_ddr_addr_dec()
1042 for (j = 0; j < 11; j++) { in cal_ddr_addr_dec()
1053 for (j = 0; j < 2; j++) { in cal_ddr_addr_dec()
1064 for (j = 0; j < 2; j++) { in cal_ddr_addr_dec()
1075 for (j = 0; j < 2; j++) { in cal_ddr_addr_dec()
1149 int i, j, k; in skip_caslat() local
1293 for (j = 0; j < 4; j++) { in skip_caslat()
1300 if (j >= 4) { in skip_caslat()
1306 (bin[i].taamin_ps[j] > taamin_ps && j > 0)) { in skip_caslat()
[all …]
A Dddr.c513 int j, valid_mask = 0; in parse_spd() local
534 for (j = 0; j < num_dimm; j++, addr_idx++) { in parse_spd()
535 debug("DIMM %d\n", j); in parse_spd()
538 if (j == 0) { in parse_spd()
576 conf->dimm_in_use[j] = 1; in parse_spd()
620 for (j = 0; j < DDRC_NUM_DIMM; j++) { in parse_spd()
621 if (conf->dimm_in_use[j] == 0) { in parse_spd()
629 conf->cs_on_dimm[j] = 0x3 << (j * CONFIG_CS_PER_SLOT); in parse_spd()
630 conf->cs_in_use |= conf->cs_on_dimm[j]; in parse_spd()
633 conf->cs_on_dimm[j] = 0x1 << (j * CONFIG_CS_PER_SLOT); in parse_spd()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/common/ddr/ddr_a/
A Dddr_init_e3.c699 for (j = 0; j < 4; j++) { in init_ddr()
700 rbd_0c[j] = rbd_0c[j] + in init_ddr()
704 regval = regval | (rbd_0c[j] << 8 * j); in init_ddr()
716 for (j = 0; j < 4; j++) { in init_ddr()
717 rbd_0c[j] = rbd_0c[j] + in init_ddr()
721 regval = regval | (rbd_0c[j] << 8 * j); in init_ddr()
1551 for (j = 0; j < 4; j++) { in recovery_from_backup_mode()
1552 rbd_0c[j] = rbd_0c[j] + in recovery_from_backup_mode()
1556 regval = regval | (rbd_0c[j] << 8 * j); in recovery_from_backup_mode()
1568 for (j = 0; j < 4; j++) { in recovery_from_backup_mode()
[all …]
/tf-a-ffa_el3_spmc/drivers/mtd/nand/
A Draw_nand.c129 uint8_t j; in nand_read_page_cmd() local
153 for (j = 0U; j < i; j++) { in nand_read_page_cmd()
154 ret = nand_send_addr(addr[j], 0U); in nand_read_page_cmd()
229 uint32_t j; in nand_check_crc() local
235 for (j = BIT(7); j != 0U; j >>= 1) { in nand_check_crc()
239 if ((cur_param & j) != 0U) { in nand_check_crc()
/tf-a-ffa_el3_spmc/tools/cert_create/src/
A Dmain.c180 int i, j; in check_cmd_params() local
220 for (j = 0; j < cert->num_ext; j++) { in check_cmd_params()
221 ext = &extensions[cert->ext[j]]; in check_cmd_params()
302 int i, j, ext_nid, nvctr; in main() local
485 for (j = 0 ; j < cert->num_ext ; j++) { in main()
487 ext = &extensions[cert->ext[j]]; in main()
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/
A Dpaxb.c704 unsigned int i, j; in paxb_ib_regs_bypass() local
724 for (j = 0; j < PAXB_MAX_IMAP_WINDOWS; j++) { in paxb_ib_regs_bypass()
725 mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP0_OFFSET(j), in paxb_ib_regs_bypass()
727 (j * PAXB_IMAP0_WINDOW_SIZE)) | in paxb_ib_regs_bypass()
789 unsigned int i, j; in paxb_cfg_coherency() local
806 for (j = 0; j < PAXB_MAX_IMAP_WINDOWS; j++) { in paxb_cfg_coherency()
808 mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP3_OFFSET(j), in paxb_cfg_coherency()
810 mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP4_OFFSET(j), in paxb_cfg_coherency()
814 mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP0_OFFSET(j), in paxb_cfg_coherency()
818 PAXB_IMAP3_0_AXUSER_OFFSET(j), in paxb_cfg_coherency()
[all …]
/tf-a-ffa_el3_spmc/plat/st/stm32mp1/
A Dstm32mp1_scmi.c450 size_t j; in stm32mp1_init_scmi_server() local
452 for (j = 0U; j < res->clock_count; j++) { in stm32mp1_init_scmi_server()
453 struct stm32_scmi_clk *clk = &res->clock[j]; in stm32mp1_init_scmi_server()
468 for (j = 0U; j < res->rstd_count; j++) { in stm32mp1_init_scmi_server()
469 struct stm32_scmi_rstd *rstd = &res->rstd[j]; in stm32mp1_init_scmi_server()
/tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/aarch64/
A Dzynqmp_common.c222 size_t i, j, len; in zynqmp_get_silicon_idcode_name() local
265 for (j = 0; j < strlen(name); j++) { in zynqmp_get_silicon_idcode_name()
266 zynqmp_devices[i].name[len] = name[j]; in zynqmp_get_silicon_idcode_name()
/tf-a-ffa_el3_spmc/lib/romlib/templates/
A Djmptbl_entry_reserved_bti.S6 bti j
A Djmptbl_entry_function_bti.S6 bti j
/tf-a-ffa_el3_spmc/services/std_svc/sdei/
A Dsdei_event.c86 unsigned int i, j; in find_event_map() local
94 iterate_mapping(mapping, j, map) { in find_event_map()
/tf-a-ffa_el3_spmc/drivers/partition/
A Dpartition.c25 int i, j, len; in dump_entries() local
30 for (j = 0; j < EFI_NAMELEN - len - 1; j++) { in dump_entries()
31 name[len + j] = ' '; in dump_entries()
/tf-a-ffa_el3_spmc/drivers/nxp/auth/csf_hdr_parser/
A Dcsf_hdr_parser.c54 int i, j = 0; in deploy_rotpk_hash_table() local
126 for (j = 0; j < 8; j++) { in deploy_rotpk_hash_table()
127 VERBOSE("%x\n", *((uint32_t *)rotpk_hash_table[i] + j)); in deploy_rotpk_hash_table()
/tf-a-ffa_el3_spmc/common/
A Dfdt_fixup.c338 unsigned int i, j, k; in fdt_add_cpus_node() local
372 for (j = afflv1; j > 0U; j--) { in fdt_add_cpus_node()
375 ((j - 1) << MPIDR_AFF1_SHIFT) | in fdt_add_cpus_node()
/tf-a-ffa_el3_spmc/drivers/measured_boot/
A Devent_print.c209 for (unsigned int j = 0U; j < sha_size; ++j) { in event2_print() local
211 if ((j & U(0xF)) == U(0xF)) { in event2_print()
213 if (j < (sha_size - 1U)) { in event2_print()

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