Home
last modified time | relevance | path

Searched refs:lvl (Results 1 – 24 of 24) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/common/
A Dplat_pm.c51 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_off() argument
72 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_suspend() argument
94 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_resume() argument
218 uint32_t lvl; in rockchip_pwr_domain_off() local
231 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_off()
245 uint32_t lvl; in rockchip_pwr_domain_suspend() local
267 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend()
282 uint32_t lvl; in rockchip_pwr_domain_on_finish() local
288 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_on_finish()
319 uint32_t lvl; in rockchip_pwr_domain_suspend_finish() local
[all …]
/tf-a-ffa_el3_spmc/lib/psci/
A Dpsci_stat.c79 unsigned int lvl, parent_idx; in psci_stats_update_pwr_down() local
87 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_down()
90 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) in psci_stats_update_pwr_down()
112 unsigned int lvl, parent_idx; in psci_stats_update_pwr_up() local
142 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_up()
143 local_state = state_info->pwr_domain_state[lvl]; in psci_stats_update_pwr_up()
152 residency = plat_psci_stat_get_residency(lvl, state_info, in psci_stats_update_pwr_up()
159 stat_idx = get_stat_idx(local_state, lvl); in psci_stats_update_pwr_up()
179 unsigned int pwrlvl, lvl, parent_idx, target_idx; in psci_get_stat() local
213 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++) in psci_get_stat()
A Dpsci_common.c308 unsigned int parent_idx, lvl; in psci_get_target_local_pwr_states() local
315 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_get_target_local_pwr_states()
321 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_get_target_local_pwr_states()
334 unsigned int parent_idx, lvl; in psci_set_target_local_pwr_states() local
348 for (lvl = 1U; lvl <= end_pwrlvl; lvl++) { in psci_set_target_local_pwr_states()
384 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_set_pwr_domains_to_run()
387 psci_set_req_local_pwr_state(lvl, in psci_set_pwr_domains_to_run()
433 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_do_state_coordination()
436 psci_set_req_local_pwr_state(lvl, cpu_idx, in psci_do_state_coordination()
467 for (lvl = lvl + 1U; lvl <= end_pwrlvl; lvl++) { in psci_do_state_coordination()
[all …]
A Dpsci_off.c24 unsigned int lvl; in psci_set_power_off_state() local
26 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_set_power_off_state()
27 state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE; in psci_set_power_off_state()
/tf-a-ffa_el3_spmc/plat/socionext/synquacer/drivers/scp/
A Dsq_scmi.c102 int lvl = 0, ret; in sq_scmi_off() local
109 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in sq_scmi_off()
110 if (target_state->pwr_domain_state[lvl] == SQ_LOCAL_STATE_RUN) in sq_scmi_off()
113 assert(target_state->pwr_domain_state[lvl] == in sq_scmi_off()
115 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, in sq_scmi_off()
119 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); in sq_scmi_off()
138 int lvl = 0, ret, core_pos; in sq_scmi_on() local
141 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) in sq_scmi_on()
142 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, in sq_scmi_on()
145 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); in sq_scmi_on()
/tf-a-ffa_el3_spmc/drivers/arm/css/scp/
A Dcss_pm_scmi.c130 unsigned int lvl, channel_id, domain_id; in css_scp_suspend() local
142 for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in css_scp_suspend()
146 assert(target_state->pwr_domain_state[lvl] == in css_scp_suspend()
152 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, in css_scp_suspend()
177 unsigned int lvl = 0, channel_id, domain_id; in css_scp_off() local
188 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in css_scp_off()
192 assert(target_state->pwr_domain_state[lvl] == in css_scp_off()
194 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, in css_scp_off()
217 unsigned int lvl = 0, channel_id, core_pos, domain_id; in css_scp_on() local
221 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) in css_scp_on()
[all …]
/tf-a-ffa_el3_spmc/plat/common/
A Dplat_psci_common.c92 u_register_t plat_psci_stat_get_residency(unsigned int lvl, in plat_psci_stat_get_residency() argument
100 assert((lvl >= PSCI_CPU_PWR_LVL) && (lvl <= PLAT_MAX_PWR_LVL)); in plat_psci_stat_get_residency()
104 if (lvl == PSCI_CPU_PWR_LVL) in plat_psci_stat_get_residency()
148 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, in plat_get_target_pwr_state() argument
/tf-a-ffa_el3_spmc/plat/rockchip/common/include/
A Dplat_private.h112 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
117 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
119 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
124 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A Dplat_psci_handlers.c101 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, in tegra_soc_get_target_pwr_state() argument
112 if (lvl == MPIDR_AFFLVL1) in tegra_soc_get_target_pwr_state()
114 if (lvl == MPIDR_AFFLVL2) in tegra_soc_get_target_pwr_state()
117 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { in tegra_soc_get_target_pwr_state()
175 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && in tegra_soc_get_target_pwr_state()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/
A Dtegra_pm.c324 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, in plat_get_target_pwr_state() argument
328 return tegra_soc_get_target_pwr_state(lvl, states, ncpu); in plat_get_target_pwr_state()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/
A Dplat_psci_handlers.c242 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, in tegra_soc_get_target_pwr_state() argument
250 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
255 if (lvl == (uint32_t)MPIDR_AFFLVL1) { in tegra_soc_get_target_pwr_state()
/tf-a-ffa_el3_spmc/include/plat/common/
A Dplatform.h267 u_register_t plat_psci_stat_get_residency(unsigned int lvl,
270 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/
A Dplat_psci_handlers.c257 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, in tegra_soc_get_target_pwr_state() argument
265 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && in tegra_soc_get_target_pwr_state()
271 if (lvl == (uint32_t)MPIDR_AFFLVL1) { in tegra_soc_get_target_pwr_state()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/
A Dtegra_private.h118 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
/tf-a-ffa_el3_spmc/plat/nxp/common/psci/
A Dplat_psci.c343 int lvl = (pwr_state & PWR_STATE_LVL_MASK); in _pwr_state_validate() local
345 switch (lvl) { in _pwr_state_validate()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/pmu/
A Dpmu.c670 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_off() argument
673 if (lvl == MPIDR_AFFLVL1) { in rockchip_soc_hlvl_pwr_dm_off()
695 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state) in rockchip_soc_hlvl_pwr_dm_suspend() argument
697 if (lvl == MPIDR_AFFLVL1) { in rockchip_soc_hlvl_pwr_dm_suspend()
713 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, in rockchip_soc_hlvl_pwr_dm_on_finish() argument
716 if (lvl == MPIDR_AFFLVL1) { in rockchip_soc_hlvl_pwr_dm_on_finish()
733 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state) in rockchip_soc_hlvl_pwr_dm_resume() argument
735 if (lvl == MPIDR_AFFLVL1) { in rockchip_soc_hlvl_pwr_dm_resume()
/tf-a-ffa_el3_spmc/fdts/
A Dfvp-foundation-gicv2-psci.dts46 max-pwr-lvl = <2>;
A Dfvp-foundation-gicv3-psci.dts46 max-pwr-lvl = <2>;
A Dfvp-base-gicv2-psci.dts45 max-pwr-lvl = <2>;
A Dfvp-base-gicv2-psci-aarch32.dts46 max-pwr-lvl = <2>;
A Dfvp-base-gicv3-psci-aarch32-common.dtsi38 max-pwr-lvl = <2>;
A Dfvp-base-gicv3-psci-common.dtsi44 max-pwr-lvl = <2>;
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/
A Dplat_pm.c588 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, in plat_get_target_pwr_state() argument
/tf-a-ffa_el3_spmc/docs/getting_started/
A Dporting-guide.rst2192 identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2211 power domain level ``lvl`` (first argument) within the power domain. The function

Completed in 36 milliseconds