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/tf-a-ffa_el3_spmc/tools/memory/
A Dprint_memory_map.py52 match = line_pattern.search(line) variable
53 if match:
55 match = address_pattern.search(line) variable
56 if match:
57 address_list.append([match.group(0), symbol, image])
/tf-a-ffa_el3_spmc/lib/zlib/
A Dinftrees.c57 unsigned match; /* use base and extra for symbol >= match */ local
184 match = 20;
189 match = 257;
194 match = 0;
217 if (work[sym] + 1U < match) {
221 else if (work[sym] >= match) {
222 here.op = (unsigned char)(extra[work[sym] - match]);
223 here.val = base[work[sym] - match];
/tf-a-ffa_el3_spmc/plat/intel/soc/common/soc/
A Dsocfpga_reset_manager.c90 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match) in poll_idle_status() argument
95 if ((mmio_read_32(addr) & mask) == match) { in poll_idle_status()
/tf-a-ffa_el3_spmc/
A D.editorconfig20 # set default to match [LCS] .c/.h settings.
/tf-a-ffa_el3_spmc/fdts/
A Darm_fpga.dts98 /* The GICR size will be adjusted at runtime to match the cores. */
/tf-a-ffa_el3_spmc/docs/plat/
A Dallwinner.rst89 address space. So the virtual addresses used in BL31 match the physical
A Drpi3.rst62 between them so that the addresses they are loaded to match the ones specified
197 The build system concatenates BL1 and the FIP so that the addresses match the
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/scat/
A Dbl31.scat197 /* PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements */
/tf-a-ffa_el3_spmc/docs/components/fconf/
A Dindex.rst73 Then, a wrapper has to be provided to match the ``FCONF_GET_PROPERTY()`` macro:
/tf-a-ffa_el3_spmc/docs/design/
A Dtrusted-board-boot.rst145 registers. If they match, the BL2 hash is read from the certificate.
188 if the hashes match.
A Dreset-design.rst104 BL31 is loaded to its runtime address, which must match the CPU's ``RVBAR_EL3``
A Dauth-framework.rst506 auth_param_type_desc_t *hash; /* Hash to match with */
652 CoT array, so the descriptors location in the array must match the identifiers.
684 - ``AUTH_METHOD_HASH``: the hash of the image must match the hash extracted
A Dfirmware-design.rst1496 - And the errata identifier: the identifier must match what's used in the
/tf-a-ffa_el3_spmc/docs/plat/arm/fvp/
A Dindex.rst102 required to match the run time characteristics of the older versions.
226 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
402 versions must match. The Foundation FVP defaults to the highest v8.x
/tf-a-ffa_el3_spmc/docs/components/
A Dexception-handling.rst110 priority of the acknowledged interrupt is used to match its registered handler.
239 priority of secure interrupts must match that as determined in the
613 dispatcher match. The |EHF| cannot verify that this has been followed.
/tf-a-ffa_el3_spmc/docs/plat/arm/
A Darm-build-options.rst16 should match the frame used by the Non-Secure image (normally the Linux
/tf-a-ffa_el3_spmc/docs/plat/arm/juno/
A Dindex.rst43 match the uboot image packaged as BL33 in the corresponding fip file. It is
/tf-a-ffa_el3_spmc/docs/process/
A Dcontributing.rst57 ``Signed-off-by:`` and ``Commit:`` lines must match. By adding this line the
A Dcoding-guidelines.rst172 | ``vsnprintf`` | Caution | inspect va_list match types |
/tf-a-ffa_el3_spmc/docs/
A Dchange-log.rst514 - Update error codes to match Linux and PMU Firmware
2026 Drop _ADDRESS from K3_USART_BASE to match other defines, Remove MSMC port
2736 match AArch32 and AArch64 type sizes
3976 match. This behaviour has been made consistent across the debug and release

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