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Searched refs:mmio_clrbits_32 (Results 1 – 25 of 96) sorted by relevance

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/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/spmc/
A Dmtspmc.c45 mmio_clrbits_32(reg, SW_NO_WAIT_Q); in spm_enable_cpu_auto_off()
65 mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q); in spm_enable_cluster_auto_off()
66 mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0)); in spm_enable_cluster_auto_off()
170 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
171 mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
274 mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), in spm_poweroff_cluster()
279 mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask); in spm_poweroff_cluster()
325 mmio_clrbits_32(MCUCFG_MP2_PWR_RST_CTL, SW_RST_B); in spm_poweron_cluster()
329 mmio_clrbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO); in spm_poweron_cluster()
341 mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), in spm_poweron_cluster()
[all …]
/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_a64/
A Dsunxi_power.c46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); in sunxi_turn_off_soc()
47 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); in sunxi_turn_off_soc()
53 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); in sunxi_turn_off_soc()
61 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); in sunxi_turn_off_soc()
62 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); in sunxi_turn_off_soc()
76 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); in sunxi_turn_off_soc()
79 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31)); in sunxi_turn_off_soc()
82 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31)); in sunxi_turn_off_soc()
83 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31)); in sunxi_turn_off_soc()
/tf-a-ffa_el3_spmc/plat/imx/imx8m/
A Dgpc_common.c60 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_on()
65 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
76 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
93 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
96 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
117 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
118 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
121 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
134 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby()
164 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); in imx_set_cluster_powerdown()
[all …]
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mq/
A Dgpc.c47 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
69 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
70 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
71 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
104 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
115 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK); in imx_set_cluster_powerdown()
169 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK); in imx_gpc_init()
176 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
177 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/spmc/
A Dmtspmc.c25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup()
53 mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
101 mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
102 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
103 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
129 mmio_clrbits_32(cpu_pwr_con, PWR_ON); in spm_poweron_cpu()
143 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/spmc/
A Dmtspmc.c25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup()
53 mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
109 mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
110 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
111 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
137 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN); in spm_poweron_cpu()
141 mmio_clrbits_32(LAST_PC_REG(cpu), BIT(3)); in spm_poweron_cpu()
154 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
/tf-a-ffa_el3_spmc/plat/intel/soc/stratix10/soc/
A Ds10_memory_controller.c160 mmio_clrbits_32(S10_CCU_CPU0_MPRT_DDR, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
161 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
162 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
163 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
164 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
168 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
169 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
170 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
171 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
172 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
[all …]
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/driver/
A Dusb_phy.c83 mmio_clrbits_32(u2_phy->phy_ctrl_reg, in u2_phy_ext_fsm_power_on()
145 mmio_clrbits_32(base + USB3H_U2PLL_CTRL, in usb3h_u2_phy_power_on()
170 mmio_clrbits_32(base + USB3H_U3PHY_PLL_CTRL, in usb3h_u3_phy_power_on()
201 mmio_clrbits_32(base + DRDU3_U2PLL_CTRL, in drdu3_u2_phy_power_on()
228 mmio_clrbits_32(base + DRDU3_U3PHY_PLL_CTRL, in drdu3_u3_phy_power_on()
259 mmio_clrbits_32(base + DRDU2_U2PLL_CTRL, in drdu2_u2_phy_power_on()
288 mmio_clrbits_32(phy->drdu2reg + DRDU2_PHY_CTRL, in u3h_u2drd_phy_reset()
330 mmio_clrbits_32(phy->usb3hreg + USB3H_PWR_CTRL, in u3h_u2drd_phy_power_on()
334 mmio_clrbits_32(phy->usb3hreg + USB3H_PWR_CTRL, in u3h_u2drd_phy_power_on()
349 mmio_clrbits_32(phy->usb3hreg + DRDU2_PWR_CTRL, in u3h_u2drd_phy_power_on()
[all …]
/tf-a-ffa_el3_spmc/plat/allwinner/common/
A Dsunxi_cpu_ops.c57 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_off()
62 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_off()
75 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on()
77 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on()
84 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); in sunxi_cpu_on()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/
A Dhikey960_bl1_setup.c114 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
119 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset()
120 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset()
146 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
152 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
153 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset()
154 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
A Dhikey960_bl2_setup.c89 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
94 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset()
95 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset()
121 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
127 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
128 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset()
129 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
/tf-a-ffa_el3_spmc/plat/intel/soc/common/soc/
A Dsocfpga_reset_manager.c18 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST), in deassert_peripheral_reset()
37 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in deassert_peripheral_reset()
47 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in deassert_peripheral_reset()
71 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), in deassert_peripheral_reset()
108 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0); in socfpga_bridges_enable()
143 mmio_clrbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); in socfpga_bridges_disable()
A Dsocfpga_emac.c28 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), in socfpga_emac_init()
33 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in socfpga_emac_init()
/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/
A Dscu.c25 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, in enable_scu()
28 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config, in enable_scu()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/
A Dscu.c25 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, in enable_scu()
28 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, in enable_scu()
/tf-a-ffa_el3_spmc/drivers/brcm/
A Dsotp.c84 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
106 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_read()
124 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
177 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
185 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
216 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
248 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
252 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
A Drng.c32 mmio_clrbits_32(RNG_CTRL_REG, RNG_CTRL_MASK); in rng_reset()
38 mmio_clrbits_32(RNG_SOFT_RESET_REG, RNG_SOFT_RESET_MASK); in rng_reset()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/m0/src/
A Dsuspend.c27 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); in m0_main()
55 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
A Ddram.c31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in deidle_port()
77 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main()
78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mm/
A Dgpc.c44 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | in imx_gpc_init()
86 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
87 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
/tf-a-ffa_el3_spmc/plat/intel/soc/common/drivers/ccu/
A Dncore_ccu.c100 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1), in bypass_ocram_firewall()
102 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2), in bypass_ocram_firewall()
104 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3), in bypass_ocram_firewall()
106 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4), in bypass_ocram_firewall()
/tf-a-ffa_el3_spmc/drivers/st/gpio/
A Dstm32_gpio.c213 mmio_clrbits_32(base + GPIO_MODE_OFFSET, in set_gpio()
221 mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); in set_gpio()
224 mmio_clrbits_32(base + GPIO_SPEED_OFFSET, in set_gpio()
228 mmio_clrbits_32(base + GPIO_PUPD_OFFSET, in set_gpio()
233 mmio_clrbits_32(base + GPIO_AFRL_OFFSET, in set_gpio()
238 mmio_clrbits_32(base + GPIO_AFRH_OFFSET, in set_gpio()
281 mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); in set_gpio_secure_cfg()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/dram/
A Dsuspend.c258 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); in data_training()
304 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); in data_training()
352 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); in data_training()
385 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); in data_training()
399 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); in data_training()
420 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); in data_training()
424 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training()
772 mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10); in phy_dll_bypass_set()
773 mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10); in phy_dll_bypass_set()
774 mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10); in phy_dll_bypass_set()
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/mtcmos/
A Dmtcmos.c138 mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); in mtcmos_ctrl_little_off()
144 mmio_clrbits_32(reg_pwr_con, PWR_RST_B); in mtcmos_ctrl_little_off()
146 mmio_clrbits_32(reg_pwr_con, PWR_ON); in mtcmos_ctrl_little_off()
147 mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); in mtcmos_ctrl_little_off()
270 mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); in mtcmos_non_cpu_ctrl()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/spm/
A Dspm_suspend.c285 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); in bigcore_pll_on()
291 mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); in bigcore_pll_off()
293 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); in bigcore_pll_off()

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