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Searched refs:mmio_clrsetbits_32 (Results 1 – 25 of 62) sorted by relevance

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/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/driver/ext_sram_init/
A Dext_sram_init.c24 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2dc), in brcm_stingray_pnor_pinmux_init()
29 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e0), in brcm_stingray_pnor_pinmux_init()
34 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e4), in brcm_stingray_pnor_pinmux_init()
39 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e8), in brcm_stingray_pnor_pinmux_init()
44 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2ec), in brcm_stingray_pnor_pinmux_init()
49 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f0), in brcm_stingray_pnor_pinmux_init()
54 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f4), in brcm_stingray_pnor_pinmux_init()
59 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f8), in brcm_stingray_pnor_pinmux_init()
64 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2fc), in brcm_stingray_pnor_pinmux_init()
69 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x300), in brcm_stingray_pnor_pinmux_init()
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/dcm/
A Dmtk_dcm_utils.c63 mmio_clrsetbits_32(MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
66 mmio_clrsetbits_32(MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
69 mmio_clrsetbits_32(MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
123 mmio_clrsetbits_32(MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
134 mmio_clrsetbits_32(MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
189 mmio_clrsetbits_32(MP0_DCM_CFG7, in dcm_mp_cpusys_top_core_stall_dcm()
194 mmio_clrsetbits_32(MP0_DCM_CFG7, in dcm_mp_cpusys_top_core_stall_dcm()
219 mmio_clrsetbits_32(MCSI_DCM0, in dcm_mp_cpusys_top_cpubiu_dcm()
224 mmio_clrsetbits_32(MCSI_DCM0, in dcm_mp_cpusys_top_cpubiu_dcm()
552 mmio_clrsetbits_32(EMI_WFIFO, in dcm_cpccfg_reg_emi_wfifo()
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/dcm/
A Dmtk_dcm_utils.c63 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
66 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
69 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
123 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
134 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
195 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, in dcm_mp_cpusys_top_core_stall_dcm()
200 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, in dcm_mp_cpusys_top_core_stall_dcm()
225 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, in dcm_mp_cpusys_top_cpubiu_dcm()
230 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, in dcm_mp_cpusys_top_cpubiu_dcm()
474 mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, in dcm_cpccfg_reg_emi_wfifo()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/dram/
A Ddfs.c500 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, in gen_rk3399_ctl_params_f0()
547 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, in gen_rk3399_ctl_params_f0()
549 mmio_clrsetbits_32(CTL_REG(i, 39), in gen_rk3399_ctl_params_f0()
582 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, in gen_rk3399_ctl_params_f0()
661 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, in gen_rk3399_ctl_params_f0()
797 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, in gen_rk3399_ctl_params_f1()
831 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, in gen_rk3399_ctl_params_f1()
836 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, in gen_rk3399_ctl_params_f1()
1166 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, in gen_rk3399_pi_params_f0()
1192 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, in gen_rk3399_pi_params_f0()
[all …]
A Dsuspend.c175 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), in override_write_leveling_value()
228 mmio_clrsetbits_32(PI_REG(ch, 92), in data_training()
268 mmio_clrsetbits_32(PI_REG(ch, 59), in data_training()
312 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, in data_training()
318 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
360 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 16, in data_training()
363 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
401 mmio_clrsetbits_32(PI_REG(ch, 124), 0x3 << 16, in data_training()
404 mmio_clrsetbits_32(PI_REG(ch, 121), in data_training()
604 mmio_clrsetbits_32(PHY_REG(0, 957), 0x3 << 24, in pctl_start()
[all …]
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/
A Dsdio.c70 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_CLK, in brcm_stingray_sdio_init()
72 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA0, in brcm_stingray_sdio_init()
74 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA1, in brcm_stingray_sdio_init()
76 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA2, in brcm_stingray_sdio_init()
78 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA3, in brcm_stingray_sdio_init()
80 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA4, in brcm_stingray_sdio_init()
82 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA5, in brcm_stingray_sdio_init()
84 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA6, in brcm_stingray_sdio_init()
88 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_CMD, in brcm_stingray_sdio_init()
122 mmio_clrsetbits_32(sdio1_cfg->pad_base + PAD_SDIO_CLK, in brcm_stingray_sdio_init()
[all …]
A Dbl31_setup.c328 mmio_clrsetbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_SPEED_MASK, in brcm_stingray_amac_init()
340 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_ARCACHE_MASK, in brcm_stingray_amac_init()
342 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_AWCACHE_MASK, in brcm_stingray_amac_init()
501 mmio_clrsetbits_32(scr_base + 0x0, clr_mask, set_mask); in brcm_stingray_scr_init()
506 mmio_clrsetbits_32(scr_base + 0x4, clr_mask, set_mask); in brcm_stingray_scr_init()
511 mmio_clrsetbits_32(scr_base + 0x8, clr_mask, set_mask); in brcm_stingray_scr_init()
516 mmio_clrsetbits_32(scr_base + 0xc, clr_mask, set_mask); in brcm_stingray_scr_init()
521 mmio_clrsetbits_32(scr_base + 0x10, clr_mask, set_mask); in brcm_stingray_scr_init()
592 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_ARCACHE_MASK, in brcm_stingray_audio_init()
595 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_AWCACHE_MASK, in brcm_stingray_audio_init()
A Dncsi.c49 mmio_clrsetbits_32((NITRO_NCSI_IOPAD_CONTROL_BASE + (i * 4)), in brcm_stingray_ncsi_init()
/tf-a-ffa_el3_spmc/plat/intel/soc/common/soc/
A Dsocfpga_emac.c21 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_0), in socfpga_emac_init()
23 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_1), in socfpga_emac_init()
25 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_2), in socfpga_emac_init()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/
A Dbl31_plat_setup.c49 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, in platform_setup_cpu()
51 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, in platform_setup_cpu()
54 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, in platform_setup_cpu()
60 mmio_clrsetbits_32( in platform_setup_cpu()
68 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, in platform_setup_cpu()
74 mmio_clrsetbits_32( in platform_setup_cpu()
A Dplat_mt_gic.c145 mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON); in mt_gic_sync_dcm_enable()
150 mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF); in mt_gic_sync_dcm_disable()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/devapc/
A Ddevapc.c46 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain()
60 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
66 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
71 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
75 mmio_clrsetbits_32(base, 0x1, set_bit); in set_master_domain_remap_infra()
90 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_mm()
116 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_module_apc()
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/driver/
A Dusb.c183 mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIWRA, in usb_enable_coherence()
187 mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIRDA, in usb_enable_coherence()
191 mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIWRA, in usb_enable_coherence()
195 mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIRDA, in usb_enable_coherence()
209 mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIWRA, in usb_enable_coherence()
213 mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIRDA, in usb_enable_coherence()
217 mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIWRA, in usb_enable_coherence()
221 mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIRDA, in usb_enable_coherence()
/tf-a-ffa_el3_spmc/drivers/marvell/mochi/
A Dapn806_setup.c100 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */ in apn_sec_masters_access_en()
106 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
113 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
118 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
187 mmio_clrsetbits_32(stream_id_reg[i], mask, in ap806_stream_id_init()
A Dap807_setup.c105 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */ in ap_sec_masters_access_en()
111 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
118 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
123 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
193 mmio_clrsetbits_32(stream_id_reg[i], mask, in ap807_stream_id_init()
/tf-a-ffa_el3_spmc/plat/allwinner/common/
A Dsunxi_common.c102 mmio_clrsetbits_32(port_base + (pin / 8) * 4, in sunxi_set_gpio_out()
140 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); in sunxi_init_platform_r_twi()
143 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); in sunxi_init_platform_r_twi()
146 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); in sunxi_init_platform_r_twi()
/tf-a-ffa_el3_spmc/plat/imx/imx8m/
A Dgpc_common.c144 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, in imx_set_cluster_powerdown()
163 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); in imx_set_cluster_powerdown()
167 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), in imx_set_cluster_powerdown()
190 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), in imx_set_sys_wakeup()
193 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, in imx_set_sys_wakeup()
/tf-a-ffa_el3_spmc/include/drivers/nxp/dcfg/
A Dscfg.h46 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
53 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/spm/
A Dspm_hotplug.c251 mmio_clrsetbits_32(SPM_PCM_RESERVE, in spm_hotplug_on()
271 mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK, in spm_hotplug_off()
/tf-a-ffa_el3_spmc/plat/st/stm32mp1/
A Dstm32mp1_context.c27 mmio_clrsetbits_32(bkpr_itf_idx, in stm32_save_boot_interface()
/tf-a-ffa_el3_spmc/plat/intel/soc/stratix10/soc/
A Ds10_memory_controller.c226 mmio_clrsetbits_32( in configure_ddr_sched_ctrl_regs()
376 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_DDRIOCTRL, in configure_hmc_adaptor_regs()
385 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
392 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL2, in configure_hmc_adaptor_regs()
399 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/include/
A Dsr_utils.h33 mmio_clrsetbits_32(CDRU_CHIP_STRAP_DATA, in brcm_stingray_set_straps()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/ptp3/
A Dmtk_ptp3_common.h35 mmio_clrsetbits_32((uintptr_t)addr, clear, set)
/tf-a-ffa_el3_spmc/plat/intel/soc/agilex/soc/
A Dagilex_memory_controller.c197 mmio_clrsetbits_32( in configure_ddr_sched_ctrl_regs()
373 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
380 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL2, in configure_hmc_adaptor_regs()
387 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/m0/include/
A Drk3399_mcu.h22 #define mmio_clrsetbits_32(addr, clear, set) \ macro

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