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Searched refs:mmio_setbits_32 (Results 1 – 25 of 106) sorted by relevance

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/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/spmc/
A Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
113 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in spmc_init()
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/spmc/
A Dmtspmc.c51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
105 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in spmc_init()
126 mmio_setbits_32(cpu_pwr_con, PWR_ON); in spm_poweron_cpu()
[all …]
/tf-a-ffa_el3_spmc/plat/marvell/armada/a3k/common/
A Dplat_pm.c349 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
350 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
383 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_SR_EN); in a3700_en_ddr_self_refresh()
388 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, in a3700_en_ddr_self_refresh()
426 mmio_setbits_32(MVEBU_AVS_CTRL_2_REG, MVEBU_LOW_VDD_MODE_EN); in a3700_pwr_dn_avs()
438 mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_SB_PWR_DWN); in a3700_pwr_dn_sb()
482 mmio_setbits_32(MVEBU_PM_CPU_WAKE_UP_CONF_REG, in a3700_set_wake_up_option()
503 mmio_setbits_32(MVEBU_NB_GPIO_IRQ_EN_LOW_REG, BIT(gpio)); in a3700_pm_en_nb_gpio()
506 mmio_setbits_32(MVEBU_NB_STEP_DOWN_INT_EN_REG, in a3700_pm_en_nb_gpio()
532 mmio_setbits_32(MVEBU_SB_GPIO_IRQ_EN_REG, BIT(gpio)); in a3700_pm_en_sb_gpio()
[all …]
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/driver/
A Dusb.c31 mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, in usb_pm_rescal_init()
63 mmio_setbits_32(USB3H_U3PHY_CTRL, PHY_RESET); in usb3h_usb2drd_init()
70 mmio_setbits_32(USB3H_U3PHY_CTRL, MDIO_RESET); in usb3h_usb2drd_init()
116 mmio_setbits_32(DRDU3_U3PHY_CTRL, PHY_RESET); in usb3drd_init()
123 mmio_setbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET); in usb3drd_init()
176 mmio_setbits_32(USB3H_SOFT_RESET_CTRL, in usb_enable_coherence()
178 mmio_setbits_32(DRDU2_SOFT_RESET_CTRL, in usb_enable_coherence()
202 mmio_setbits_32(DRDU3_SOFT_RESET_CTRL, in usb_enable_coherence()
205 mmio_setbits_32(DRDU3_U3PHY_CTRL, in usb_enable_coherence()
233 mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL, in xhci_phy_init()
[all …]
A Dusb_phy.c75 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO); in u2_phy_ext_fsm_power_on()
284 mmio_setbits_32(phy->usb3hreg + USB3H_U2PHY_CTRL, in u3h_u2drd_phy_reset()
290 mmio_setbits_32(phy->drdu2reg + DRDU2_PHY_CTRL, in u3h_u2drd_phy_reset()
303 mmio_setbits_32(phy->drdu3reg + DRDU3_U2PHY_CTRL, in u3drd_phy_reset()
325 mmio_setbits_32(AXI_DEBUG_CTRL, in u3h_u2drd_phy_power_on()
327 mmio_setbits_32(USB3H_DEBUG_CTRL, in u3h_u2drd_phy_power_on()
344 mmio_setbits_32(AXI_DEBUG_CTRL, in u3h_u2drd_phy_power_on()
346 mmio_setbits_32(USB3H_DEBUG_CTRL, in u3h_u2drd_phy_power_on()
369 mmio_setbits_32(phy->drdu2reg + DRDU2_PHY_CTRL, in u3h_u2drd_phy_power_on()
404 mmio_setbits_32(AXI_DEBUG_CTRL, in u3drd_phy_power_on()
[all …]
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/
A Dbl31_setup.c267 mmio_setbits_32(CRMU_AON_CTRL1, in poweroff_sata_pll()
355 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_pka_meminit()
362 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_pka_meminit()
369 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_pka_meminit()
376 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_pka_meminit()
437 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_dma_pl330_meminit()
444 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_dma_pl330_meminit()
451 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_dma_pl330_meminit()
458 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_dma_pl330_meminit()
608 mmio_setbits_32(icfg_mem_ctrl, in brcm_stingray_audio_init()
[all …]
A Dihost_pm.c152 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, rst); in ihost_power_on_cluster()
178 mmio_setbits_32(CRMU_BISR_PDG_MASK, (1 << bisr)); in ihost_power_on_cluster()
233 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
256 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_0, in ihost_power_on_cluster()
268 mmio_setbits_32(CDRU_CCN_REGISTER_CONTROL_1, d2xs); in ihost_power_on_cluster()
287 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
295 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_1, in ihost_power_on_cluster()
299 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
303 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
344 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_secondary_core()
[all …]
/tf-a-ffa_el3_spmc/plat/imx/imx8m/
A Dgpc_common.c47 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_off()
52 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
67 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
69 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); in imx_set_cpu_pwr_on()
78 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
90 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
111 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
112 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
115 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
132 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby()
[all …]
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mq/
A Dgpc.c25 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_pwr_off()
31 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
41 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
44 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
50 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
60 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN); in imx_pup_pdn_slot_config()
62 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP); in imx_pup_pdn_slot_config()
64 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core)); in imx_pup_pdn_slot_config()
88 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP); in imx_set_cluster_powerdown()
101 mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/
A Dbl31_plat_setup.c42 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, in platform_setup_cpu()
44 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, in platform_setup_cpu()
46 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, in platform_setup_cpu()
57 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
65 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
71 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, in platform_setup_cpu()
78 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, in platform_setup_cpu()
81 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, in platform_setup_cpu()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/
A Dbl31_plat_setup.c40 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); in platform_setup_cpu()
41 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, in platform_setup_cpu()
47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, in platform_setup_cpu()
51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, in platform_setup_cpu()
55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, in platform_setup_cpu()
59 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
61 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
A Dscu.c15 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, in disable_scu()
18 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, in disable_scu()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/spmc/
A Dmtspmc.c52 mmio_setbits_32(reg, SW_NO_WAIT_Q); in spm_disable_cpu_auto_off()
115 mmio_setbits_32(reg, (arm64 & 1) << (i + cpu)); in mcucfg_init_archstate()
175 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
176 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
177 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
189 mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
190 mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
191 mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
192 mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
300 mmio_setbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO); in spm_poweroff_cluster()
[all …]
/tf-a-ffa_el3_spmc/drivers/brcm/
A Dsotp.c80 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
89 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
98 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_read()
121 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_read()
172 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
181 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
204 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
213 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_write()
237 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
245 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_write()
/tf-a-ffa_el3_spmc/plat/allwinner/common/
A Dsunxi_cpu_ops.c60 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); in sunxi_cpu_off()
79 mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster), in sunxi_cpu_on()
86 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on()
88 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on()
90 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_on()
A Dsunxi_common.c97 mmio_setbits_32(port_base + 0x10, BIT(pin)); in sunxi_set_gpio_out()
137 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); in sunxi_init_platform_r_twi()
150 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); in sunxi_init_platform_r_twi()
152 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0)); in sunxi_init_platform_r_twi()
156 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); in sunxi_init_platform_r_twi()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/
A Dhikey960_bl1_setup.c124 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
130 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
132 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); in hikey960_ufs_reset()
147 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, in hikey960_ufs_reset()
149 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); in hikey960_ufs_reset()
151 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); in hikey960_ufs_reset()
156 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); in hikey960_ufs_reset()
A Dhikey960_bl2_setup.c99 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
105 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
107 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); in hikey960_ufs_reset()
122 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, in hikey960_ufs_reset()
124 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); in hikey960_ufs_reset()
126 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); in hikey960_ufs_reset()
131 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); in hikey960_ufs_reset()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/dfd/
A Dplat_dfd.c25 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); in dfd_setup()
35 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3); in dfd_setup()
38 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
99 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/
A Dscu.c15 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, in disable_scu()
18 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config, in disable_scu()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/mtcmos/
A Dmtcmos.c136 mmio_setbits_32(reg_pwr_con, PWR_ISO); in mtcmos_ctrl_little_off()
137 mmio_setbits_32(reg_pwr_con, SRAM_CKISO); in mtcmos_ctrl_little_off()
139 mmio_setbits_32(reg_l1_pdn, L1_PDN); in mtcmos_ctrl_little_off()
145 mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS); in mtcmos_ctrl_little_off()
204 mmio_setbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); in mtcmos_non_cpu_ctrl()
264 mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl); in mtcmos_non_cpu_ctrl()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/m0/src/
A Ddram.c21 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in idle_port()
60 mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main()
61 mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
/tf-a-ffa_el3_spmc/plat/intel/soc/common/soc/
A Dsocfpga_reset_manager.c87 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask); in config_hps_hs_before_warm_reset()
105 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0); in socfpga_bridges_enable()
121 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); in socfpga_bridges_disable()
135 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_disable()
138 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_disable()
/tf-a-ffa_el3_spmc/drivers/st/ddr/
A Dstm32mp1_ddr.c594 mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
634 mmio_setbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
640 mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr, in stm32mp1_ddr3_dll_off()
642 mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr, in stm32mp1_ddr3_dll_off()
644 mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr, in stm32mp1_ddr3_dll_off()
676 mmio_setbits_32((uintptr_t)&ctl->rfshctl3, in stm32mp1_refresh_disable()
693 mmio_setbits_32((uintptr_t)&ctl->pwrctl, in stm32mp1_refresh_restore()
696 mmio_setbits_32((uintptr_t)&ctl->dfimisc, in stm32mp1_refresh_restore()
854 mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
908 mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_0, in stm32mp1_ddr_init()
[all …]
/tf-a-ffa_el3_spmc/drivers/st/gpio/
A Dstm32_gpio.c215 mmio_setbits_32(base + GPIO_MODE_OFFSET, in set_gpio()
219 mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); in set_gpio()
226 mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1)); in set_gpio()
230 mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1)); in set_gpio()
235 mmio_setbits_32(base + GPIO_AFRL_OFFSET, in set_gpio()
241 mmio_setbits_32(base + GPIO_AFRH_OFFSET, in set_gpio()
279 mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); in set_gpio_secure_cfg()

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