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/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/include/shared/
A Ddram_regs.h75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
79 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) argument
80 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) argument
81 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) argument
82 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) argument
83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) argument
85 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) argument
93 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16)) argument
[all …]
A Dmisc_regs.h21 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) argument
22 #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) argument
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/secure/
A Dsecure.h13 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) argument
14 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) argument
15 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) argument
16 #define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ argument
17 (n < 8 ? SGRF_SOC_CON3_7(n) :\
20 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) argument
21 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) argument
22 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) argument
23 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) argument
55 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) argument
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/
A Dsoc.h44 #define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4)) argument
67 #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) argument
73 #define GRF_SOC_CON(n) (0x400 + (n) * 4) argument
74 #define GRF_SOC_STATUS(n) (0x480 + (n) * 4) argument
75 #define GRF_CPU_STATUS(n) (0x520 + (n) * 4) argument
76 #define GRF_OS_REG(n) (0x5c8 + (n) * 4) argument
77 #define DDRGRF_SOC_CON(n) (0x000 + (n) * 4) argument
78 #define DDRGRF_SOC_STATUS(n) (0x100 + (n) * 4) argument
79 #define SGRF_SOC_CON(n) (0x000 + (n) * 4) argument
80 #define SGRF_DMAC_CON(n) (0x100 + (n) * 4) argument
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/soc/
A Dsoc.h15 #define PMUCRU_PPLL_CON(n) ((n) * 4) argument
29 #define FBDIV(n) ((0xfff << 16) | n) argument
32 #define REFDIV(n) ((0x3F << 16) | n) argument
33 #define PLL_LOCK(n) ((n >> 31) & 0x1) argument
46 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) argument
56 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) argument
57 #define CRU_GATE_CON(n) (0x300 + (n) * 4) argument
147 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) argument
176 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) argument
190 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) argument
[all …]
/tf-a-ffa_el3_spmc/drivers/arm/gic/common/
A Dgic_common.c25 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
36 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
47 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
58 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
69 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
113 unsigned int n = id >> ICFGR_SHIFT; in gicd_read_icfgr() local
124 unsigned int n = id >> NSACR_SHIFT; in gicd_read_nsacr() local
138 unsigned int n = id >> IGROUPR_SHIFT; in gicd_write_igroupr() local
171 unsigned int n = id >> ISPENDR_SHIFT; in gicd_write_ispendr() local
226 unsigned int n = id >> ICFGR_SHIFT; in gicd_write_icfgr() local
[all …]
/tf-a-ffa_el3_spmc/drivers/arm/gic/v2/
A Dgicdv2_helpers.c23 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
34 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
45 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
56 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
67 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
111 unsigned int n = id >> ICFGR_SHIFT; in gicd_read_icfgr() local
122 unsigned int n = id >> NSACR_SHIFT; in gicd_read_nsacr() local
136 unsigned int n = id >> IGROUPR_SHIFT; in gicd_write_igroupr() local
169 unsigned int n = id >> ISPENDR_SHIFT; in gicd_write_ispendr() local
224 unsigned int n = id >> ICFGR_SHIFT; in gicd_write_icfgr() local
[all …]
/tf-a-ffa_el3_spmc/lib/compiler-rt/builtins/
A Dudivmoddi4.c28 udwords n; in __udivmoddi4() local
29 n.all = a; in __udivmoddi4()
36 if (n.s.high == 0) in __udivmoddi4()
53 *rem = n.s.low; in __udivmoddi4()
70 if (n.s.low == 0) in __udivmoddi4()
107 *rem = n.all; in __udivmoddi4()
117 r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); in __udivmoddi4()
132 return n.all; in __udivmoddi4()
135 q.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); in __udivmoddi4()
159 r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); in __udivmoddi4()
[all …]
/tf-a-ffa_el3_spmc/include/drivers/rpi3/gpio/
A Drpi3_gpio.h18 #define RPI3_GPIO_GPFSEL(n) ((n) * U(0x04)) argument
19 #define RPI3_GPIO_GPSET(n) (((n) * U(0x04)) + U(0x1C)) argument
20 #define RPI3_GPIO_GPCLR(n) (((n) * U(0x04)) + U(0x28)) argument
21 #define RPI3_GPIO_GPLEV(n) (((n) * U(0x04)) + U(0x34)) argument
23 #define RPI3_GPIO_GPPUDCLK(n) (((n) * U(0x04)) + U(0x98)) argument
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/secure/
A Dsecure.h15 #define TZPC_SRAM_SECURE_4K(n) ((n) > 0x200 ? 0x200 : (n)) argument
30 #define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4) argument
31 #define SGRF_BUSDMAC_CON(n) (0x20 + (n) * 4) argument
32 #define SGRF_CPU_CON(n) (0x40 + (n) * 4) argument
33 #define SGRF_SOC_STATUS(n) (0x100 + (n) * 4) argument
/tf-a-ffa_el3_spmc/lib/libc/
A Dsnprintf.c26 CHECK_AND_PUT_CHAR(*s, n, *chars_printed, *str); in string_print()
61 if (*chars_printed < n) { in unsigned_num_print()
115 if (n == 0U) { in vsnprintf()
117 } else if (n == 1U) { in vsnprintf()
120 n = 0U; in vsnprintf()
123 n--; in vsnprintf()
168 CHECK_AND_PUT_CHAR(s, n, chars_printed, in vsnprintf()
175 unsigned_num_print(&s, n, &chars_printed, in vsnprintf()
180 string_print(&s, n, &chars_printed, str); in vsnprintf()
221 if (n > 0U) { in vsnprintf()
[all …]
A Dstrlcat.c35 size_t n = dsize; in strlcat() local
39 while (n-- != 0 && *dst != '\0') in strlcat()
42 n = dsize - dlen; in strlcat()
44 if (n-- == 0) in strlcat()
47 if (n != 0) { in strlcat()
49 n--; in strlcat()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/ddr/
A Dddr_rk3368.h206 #define SET_NR(n) ((0x3f << (8 + 16)) | ((n - 1) << 8)) argument
207 #define SET_NO(n) ((0xf << (0 + 16)) | ((n - 1) << 0)) argument
208 #define SET_NF(n) ((n - 1) & 0x1fff) argument
209 #define SET_NB(n) ((n - 1) & 0xfff) argument
210 #define PLLMODE(n) ((0x3 << (8 + 16)) | (n << 8)) argument
218 #define DDRMSCH0_SRSTN_REQ(n) (((0x1 << 10) << 16) | (n << 10)) argument
219 #define DDRCTRL0_PSRSTN_REQ(n) (((0x1 << 3) << 16) | (n << 3)) argument
220 #define DDRCTRL0_SRSTN_REQ(n) (((0x1 << 2) << 16) | (n << 2)) argument
221 #define DDRPHY0_PSRSTN_REQ(n) (((0x1 << 1) << 16) | (n << 1)) argument
222 #define DDRPHY0_SRSTN_REQ(n) (((0x1 << 0) << 16) | (n << 0)) argument
/tf-a-ffa_el3_spmc/lib/zlib/
A Dcrc32.c91 int n, k; in make_crc_table() local
105 for (n = 0; n < (int)(sizeof(p)/sizeof(unsigned char)); n++) in make_crc_table()
109 for (n = 0; n < 256; n++) { in make_crc_table()
119 for (n = 0; n < 256; n++) { in make_crc_table()
169 int n; local
171 for (n = 0; n < 256; n++)
365 int n; local
367 for (n = 0; n < GF2_DIM; n++)
368 square[n] = gf2_matrix_times(mat, mat[n]);
377 int n; local
[all …]
/tf-a-ffa_el3_spmc/lib/debugfs/
A Ddevfip.c98 int n; in get_entry() local
101 if (n <= 0) { in get_entry()
102 return n; in get_entry()
217 if (n < 0) { in fipread()
230 n = devtab[cs.index]->read(&cs, buf, n); in fipread()
231 if (n > 0) { in fipread()
232 c->offset += n; in fipread()
235 return n; in fipread()
246 int r, n, t; in fipmount() local
259 for (n = 0; n < NR_FILES; n++) { in fipmount()
[all …]
/tf-a-ffa_el3_spmc/fdts/
A Dfvp-defs-dynamiq.dtsi27 * n - CPU number
42 thread##n { \
47 core##n { \
54 core##n { \
69 cluster##n { \
86 cluster##n { \
107 cluster##n { \
132 cluster##n { \
161 cluster##n { \
194 cluster##n { \
[all …]
/tf-a-ffa_el3_spmc/drivers/allwinner/
A Dsunxi_msgbox.c22 #define RX_IRQ(n) BIT(0 + 2 * (n)) argument
23 #define TX_IRQ(n) BIT(1 + 2 * (n)) argument
25 #define FIFO_STAT_REG(n) (0x0100 + 0x4 * (n)) argument
28 #define MSG_STAT_REG(n) (0x0140 + 0x4 * (n)) argument
31 #define MSG_DATA_REG(n) (0x0180 + 0x4 * (n)) argument
/tf-a-ffa_el3_spmc/include/plat/arm/css/common/
A Dcss_pm.h51 #define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \ argument
53 #define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
54 #define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \ argument
56 #define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_r329/include/
A Dsunxi_cpucfg.h20 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
21 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
26 (c) * 0x10 + (n) * 4)
/tf-a-ffa_el3_spmc/include/drivers/auth/
A Dauth_mod.h67 #define DEFINE_SIP_SP_PKG(n) DEFINE_SP_PKG(n, sip_sp_content_cert) argument
68 #define DEFINE_PLAT_SP_PKG(n) DEFINE_SP_PKG(n, plat_sp_content_cert) argument
70 #define DEFINE_SP_PKG(n, cert) \ argument
71 static const auth_img_desc_t sp_pkg##n = { \
72 .img_id = SP_PKG##n##_ID, \
80 .hash = &sp_pkg##n##_hash \
/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_h6/include/
A Dsunxi_cpucfg.h19 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
20 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
24 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
25 (c) * 0x10 + (n) * 4)
/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_h616/include/
A Dsunxi_cpucfg.h19 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
20 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
24 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
25 (c) * 0x10 + (n) * 4)
/tf-a-ffa_el3_spmc/plat/arm/css/sgi/include/
A Dsgi_base_platform_def.h25 #define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) ((ULL(1) << 42) * (n)) argument
155 #define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \ argument
157 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
163 #define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \ argument
165 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
171 #define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \ argument
173 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
253 #define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \ argument
254 {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
255 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
[all …]
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/common/include/
A Da8k_plat_def.h50 #define MVEBU_CP_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ argument
51 0x440000 + ((n) << 2))
52 #define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ argument
53 0x440000 + ((n / 8) << 2))
54 #define MVEBU_CP_GPIO_DATA_OUT(cp_index, n) \ argument
56 0x440100 + ((n > 31) ? 0x40 : 0x00))
57 #define MVEBU_CP_GPIO_DATA_OUT_EN(cp_index, n) \ argument
59 0x440104 + ((n > 31) ? 0x40 : 0x00))
60 #define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ argument
61 0x440110 + ((n > 31) ? 0x40 : 0x00))
[all …]
/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_a64/include/
A Dsunxi_cpucfg.h22 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x00a0 + (n) * 8) argument
23 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x00a4 + (n) * 8) argument
25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \ argument
26 (c) * 16 + (n) * 4)

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