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/tf-a-ffa_el3_spmc/drivers/nxp/ddr/nxp-ddr/
A DREADME.odt14 | | | |Rank 1| off | 60 | 240 | off | 60 | 240 | 60 | 60 …
16 | | | |Rank 2| off | 60 | 60 | 240 | 240 | off | 60 | 60 …
18 | | | |Rank 1| off | 60 | 60 | 60 | 60 | 60 | 240 | off …
20 | | | |Rank 2| off | 60 | 60 | 60 | 60 | 60 | 60 | 240 …
22 | | | Slot 1 | off | 60 | 80 | off | | | | …
24 | | | Slot 2 | off | 60 | | | | | 80 | off |
26 | | | |Rank 1| off | 80 | 80 | off | off | off |
28 | | | |Rank 2| off | 80 | 80 | off | off | off |
30 |Single Rank| | Slot 1 | off | 80 | 80 | off |
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/drivers/
A Dmemctrl_v2.h62 static inline uint32_t tegra_mc_read_32(uint32_t off) in tegra_mc_read_32() argument
64 return mmio_read_32(TEGRA_MC_BASE + off); in tegra_mc_read_32()
67 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) in tegra_mc_write_32() argument
69 mmio_write_32(TEGRA_MC_BASE + off, val); in tegra_mc_write_32()
73 static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) in tegra_mc_streamid_read_32() argument
75 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); in tegra_mc_streamid_read_32()
78 static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) in tegra_mc_streamid_write_32() argument
80 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); in tegra_mc_streamid_write_32()
81 assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val); in tegra_mc_streamid_write_32()
A Dsmmu.h41 static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) in tegra_smmu_read_32() argument
47 ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off); in tegra_smmu_read_32()
53 ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off); in tegra_smmu_read_32()
59 ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off); in tegra_smmu_read_32()
67 uint32_t off, uint32_t val) in tegra_smmu_write_32() argument
71 mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val); in tegra_smmu_write_32()
77 mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val); in tegra_smmu_write_32()
83 mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val); in tegra_smmu_write_32()
A Dmemctrl_v1.h47 static inline uint32_t tegra_mc_read_32(uint32_t off) in tegra_mc_read_32() argument
49 return mmio_read_32(TEGRA_MC_BASE + off); in tegra_mc_read_32()
52 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) in tegra_mc_write_32() argument
54 mmio_write_32(TEGRA_MC_BASE + off, val); in tegra_mc_write_32()
A Dpmc.h55 static inline uint32_t tegra_pmc_read_32(uint32_t off) in tegra_pmc_read_32() argument
57 return mmio_read_32(TEGRA_PMC_BASE + off); in tegra_pmc_read_32()
60 static inline void tegra_pmc_write_32(uint32_t off, uint32_t val) in tegra_pmc_write_32() argument
62 mmio_write_32(TEGRA_PMC_BASE + off, val); in tegra_pmc_write_32()
A Dflowctrl.h73 static inline uint32_t tegra_fc_read_32(uint32_t off) in tegra_fc_read_32() argument
75 return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); in tegra_fc_read_32()
78 static inline void tegra_fc_write_32(uint32_t off, uint32_t val) in tegra_fc_write_32() argument
80 mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); in tegra_fc_write_32()
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/driver/ext_sram_init/
A Dext_sram_init.c183 unsigned int off, i; in brcm_stingray_pnor_sram_init() local
262 for (off = 0; off < NOR_SIZE; off += SRAM_CHECKS_GRANUL) { in brcm_stingray_pnor_sram_init()
263 i = (off / SRAM_CHECKS_GRANUL) % SRAM_CHECKS_CNT; in brcm_stingray_pnor_sram_init()
266 (unsigned long)(NOR_BASE_ADDR + off), in brcm_stingray_pnor_sram_init()
268 mmio_write_32((uintptr_t)(NOR_BASE_ADDR + off), val); in brcm_stingray_pnor_sram_init()
271 for (off = 0; off < NOR_SIZE; off += SRAM_CHECKS_GRANUL) { in brcm_stingray_pnor_sram_init()
272 i = (off / SRAM_CHECKS_GRANUL) % SRAM_CHECKS_CNT; in brcm_stingray_pnor_sram_init()
273 val = mmio_read_32((uintptr_t)(NOR_BASE_ADDR + off)); in brcm_stingray_pnor_sram_init()
275 (unsigned long)(NOR_BASE_ADDR + off), in brcm_stingray_pnor_sram_init()
/tf-a-ffa_el3_spmc/plat/marvell/armada/a3k/common/
A Dio_addr_dec.c14 #define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \ argument
15 (win) * (off))
16 #define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \ argument
17 (win) * (off) + 0x4)
18 #define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \ argument
19 (win) * (off) + 0x8)
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/
A Dplat_smmu.c16 static uint32_t tegra_misc_read_32(uint32_t off) in tegra_misc_read_32() argument
18 return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); in tegra_misc_read_32()
/tf-a-ffa_el3_spmc/docs/resources/diagrams/plantuml/
A Dbl2-loading-sp.puml18 bl1 --> bl2 : hand off (FW_CONFIG)
40 bl2 --> bl31 : hand off (TOS_FW_CONFIG)
42 bl31 --> SPMC : hand off (TOS_FW_CONFIG)
/tf-a-ffa_el3_spmc/plat/rpi/rpi4/
A Drpi4_pci_svc.c111 uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val) in pci_read_config() argument
117 base = pci_segment_lib_get_base(addr, off); in pci_read_config()
160 uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val) in pci_write_config() argument
166 base = pci_segment_lib_get_base(addr, off); in pci_write_config()
/tf-a-ffa_el3_spmc/lib/debugfs/
A Ddevfip.c122 long off; in fipgen() local
138 off = STOC_HEADER; in fipgen()
144 if (devtab[nc.index]->seek(&nc, off, KSEEK_SET) < 0) { in fipgen()
153 off += sizeof(entry); in fipgen()
190 long off; in fipread() local
225 off = fip->offset[c->qid] + c->offset; in fipread()
226 if (devtab[cs.index]->seek(&cs, off, KSEEK_SET) < 0) { in fipread()
A Ddev.h65 int (*seek)(chan_t *c, long off, int whence);
104 int devseek(chan_t *c, long off, int whence);
114 int deverrseek(chan_t *c, long off, int whence);
A Ddev.c657 int seek(int fd, long off, int whence) in seek() argument
670 return devtab[channel->index]->seek(channel, off, whence); in seek()
695 int deverrseek(chan_t *channel, long off, int whence) in deverrseek() argument
704 int devseek(chan_t *channel, long off, int whence) in devseek() argument
708 channel->offset = off; in devseek()
711 channel->offset += off; in devseek()
/tf-a-ffa_el3_spmc/include/services/
A Dpci_svc.h45 uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val);
46 uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val);
/tf-a-ffa_el3_spmc/drivers/amlogic/crypto/
A Dsha_dma.c23 #define ASD_DESC_GET(x, msk, off) (((x) >> (off)) & (msk)) argument
24 #define ASD_DESC_SET(x, v, msk, off) \ argument
25 ((x) = ((x) & ~((msk) << (off))) | (((v) & (msk)) << (off)))
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t186/
A Dtegra_mc_def.h296 #define mc_make_txn_override_cfg(off, val) \ argument
298 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
334 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ argument
336 .name = # off, \
338 MC_STREAMID_OVERRIDE_CFG_ ## off), \
/tf-a-ffa_el3_spmc/services/std_svc/
A Dpci_svc.c16 static uint64_t validate_rw_addr_sz(uint32_t addr, uint64_t off, uint64_t sz) in validate_rw_addr_sz() argument
35 if ((off + sz) > (PCI_OFFSET_MASK + 1U)) { in validate_rw_addr_sz()
/tf-a-ffa_el3_spmc/plat/allwinner/common/
A Darisc_off.S6 # OpenRISC assembly to turn off an ARM core on an Allwinner SoC from
13 # plat/allwinner/sun50i_*/include/core_off_arisc.h, to be handed off to
18 # very ARM core to be turned off.
73 l.ori r5, r0, 0xff # 0xff means all switches off
/tf-a-ffa_el3_spmc/docs/plat/
A Ddeprecated.rst8 off period before deleting it or it can be deleted straight away. For later types
A Dls1043a.rst79 => pro off all;era 64100000 +$filesize;cp.b 82000000 64100000 $filesize
82 => pro off all;era 64120000 +$filesize;cp.b 82000000 64120000 $filesize
/tf-a-ffa_el3_spmc/lib/libfdt/
A Dfdt.c48 static int check_off_(uint32_t hdrsize, uint32_t totalsize, uint32_t off) in check_off_() argument
50 return (off >= hdrsize) && (off <= totalsize); in check_off_()
/tf-a-ffa_el3_spmc/include/lib/
A Ddebugfs.h53 int seek(int fd, long off, int whence);
/tf-a-ffa_el3_spmc/make_helpers/
A Ddefaults.mk315 SANITIZE_UB := off
/tf-a-ffa_el3_spmc/drivers/marvell/comphy/
A Dphy-comphy-3700.h251 #define SGMIIPHY_ADDR(off, base) ((((off) & 0x00007FF) * 2) + (base)) argument

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