/tf-a-ffa_el3_spmc/plat/arm/common/aarch64/ |
A D | execution_state_switch.c | 43 u_register_t spsr, pc, scr, sctlr; in arm_execution_state_switch() local 49 pc = (u_register_t) (((uint64_t) pc_hi << 32) | pc_lo); in arm_execution_state_switch() 50 if (arm_validate_ns_entrypoint(pc) != 0) in arm_execution_state_switch() 72 pc = pc_lo; in arm_execution_state_switch() 75 thumb = (pc & 1U) != 0U; in arm_execution_state_switch() 78 pc = (((u_register_t) pc_hi) << 32) | pc_lo; in arm_execution_state_switch() 82 if (((pc & 0x3U) != 0U) && !thumb) in arm_execution_state_switch() 152 ep.pc = pc; in arm_execution_state_switch()
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/tf-a-ffa_el3_spmc/plat/layerscape/common/aarch64/ |
A D | ls_bl2_mem_params_desc.c | 33 .ep_info.pc = EL3_PAYLOAD_BASE, 54 .ep_info.pc = BL31_BASE, 79 .ep_info.pc = BL32_BASE, 96 .ep_info.pc = PRELOADED_BL33_BASE, 102 .ep_info.pc = BL33_BASE,
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/tf-a-ffa_el3_spmc/lib/libc/aarch32/ |
A D | memset.S | 52 popeq {r4, pc} /* return if 0 */ 55 popeq {r4, pc} /* return if 16 */ 59 popeq {r4, pc} /* return if 8 or 4 */ 63 pop {r4, pc}
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/tf-a-ffa_el3_spmc/services/spd/tspd/ |
A D | tspd_common.c | 26 uint64_t pc, in tspd_init_tsp_ep_state() argument 34 assert(pc); in tspd_init_tsp_ep_state() 56 tsp_entry_point->pc = pc; in tspd_init_tsp_ep_state()
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/tf-a-ffa_el3_spmc/plat/brcm/common/ |
A D | brcm_bl2_mem_params_desc.c | 46 .ep_info.pc = BL31_BASE, 72 .ep_info.pc = BL32_BASE, 89 .ep_info.pc = PRELOADED_BL33_BASE, 94 .ep_info.pc = PLAT_BRCM_NS_IMAGE_OFFSET,
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/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/ |
A D | bl31_plat_setup.c | 163 if (next_image_info->pc) in bl31_plat_get_next_image_ep_info() 215 bl32_image_ep_info.pc = BL32_BASE; in bl31_early_platform_setup2() 226 bl33_image_ep_info.pc = pmtk_bl_param->bl33_start_addr; in bl31_early_platform_setup2() 356 next_image_info->pc = get_kernel_info_pc(); in bl31_plat_get_next_kernel64_ep_info() 361 next_image_info->pc, in bl31_plat_get_next_kernel64_ep_info() 369 if (next_image_info->pc) in bl31_plat_get_next_kernel64_ep_info() 400 next_image_info->pc = get_kernel_info_pc(); in bl31_plat_get_next_kernel32_ep_info() 406 next_image_info->pc, in bl31_plat_get_next_kernel32_ep_info() 415 if (next_image_info->pc) in bl31_plat_get_next_kernel32_ep_info() 445 (unsigned long long) next_image_info->pc); in bl31_prepare_kernel_entry()
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/tf-a-ffa_el3_spmc/plat/qemu/common/ |
A D | qemu_bl2_mem_params_desc.c | 28 .ep_info.pc = EL3_PAYLOAD_BASE, 45 .ep_info.pc = BL31_BASE, 78 .ep_info.pc = BL32_BASE, 132 .ep_info.pc = PRELOADED_BL33_BASE, 137 .ep_info.pc = NS_IMAGE_OFFSET,
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/tf-a-ffa_el3_spmc/services/spd/opteed/ |
A D | opteed_common.c | 23 uint32_t rw, uint64_t pc, in opteed_init_optee_ep_state() argument 32 assert(pc); in opteed_init_optee_ep_state() 46 optee_entry_point->pc = pc; in opteed_init_optee_ep_state()
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/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mm/ |
A D | imx8mm_bl2_mem_params_desc.c | 18 .ep_info.pc = BL31_BASE, 33 .ep_info.pc = BL32_BASE, 76 .ep_info.pc = PLAT_NS_IMAGE_OFFSET, 82 .ep_info.pc = PLAT_NS_IMAGE_OFFSET,
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/tf-a-ffa_el3_spmc/plat/mediatek/common/ |
A D | mtk_plat_common.c | 42 static void save_kernel_info(uint64_t pc, in save_kernel_info() argument 48 k_info.pc = pc; in save_kernel_info() 66 return k_info.pc; in get_kernel_info_pc()
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/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/ |
A D | hikey960_bl2_mem_params_desc.c | 47 .ep_info.pc = EL3_PAYLOAD_BASE, 67 .ep_info.pc = BL31_BASE, 93 .ep_info.pc = BL32_BASE, 147 .ep_info.pc = PRELOADED_BL33_BASE, 152 .ep_info.pc = NS_BL1U_BASE,
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/tf-a-ffa_el3_spmc/plat/marvell/armada/common/aarch64/ |
A D | marvell_bl2_mem_params_desc.c | 48 .ep_info.pc = EL3_PAYLOAD_BASE, 68 .ep_info.pc = BL31_BASE, 94 .ep_info.pc = BL32_BASE, 150 .ep_info.pc = PRELOADED_BL33_BASE, 155 .ep_info.pc = MARVELL_DRAM_BASE,
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/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/ |
A D | hikey_bl2_mem_params_desc.c | 47 .ep_info.pc = EL3_PAYLOAD_BASE, 67 .ep_info.pc = BL31_BASE, 93 .ep_info.pc = BL32_BASE, 147 .ep_info.pc = PRELOADED_BL33_BASE, 152 .ep_info.pc = HIKEY_NS_IMAGE_OFFSET,
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/tf-a-ffa_el3_spmc/plat/hisilicon/poplar/ |
A D | bl2_plat_mem_params_desc.c | 47 .ep_info.pc = EL3_PAYLOAD_BASE, 67 .ep_info.pc = BL31_BASE, 93 .ep_info.pc = BL32_BASE, 147 .ep_info.pc = PRELOADED_BL33_BASE, 152 .ep_info.pc = PLAT_POPLAR_NS_IMAGE_OFFSET,
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A D | bl31_plat_setup.c | 50 if (next_image_info->pc) in bl31_plat_get_next_image_ep_info() 102 if (bl33_image_ep_info.pc == 0) in bl31_early_platform_setup2() 134 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2); in bl31_plat_arch_setup()
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/tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/ |
A D | bl31_zynqmp_setup.c | 53 bl32_image_ep_info.pc = BL32_BASE; in bl31_set_default_config() 55 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in bl31_set_default_config() 122 if (bl32_image_ep_info.pc) { in bl31_early_platform_setup2() 123 VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); in bl31_early_platform_setup2() 125 if (bl33_image_ep_info.pc) { in bl31_early_platform_setup2() 126 VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); in bl31_early_platform_setup2()
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/tf-a-ffa_el3_spmc/plat/rpi/rpi3/aarch64/ |
A D | rpi3_bl2_mem_params_desc.c | 30 .ep_info.pc = BL31_BASE, 57 .ep_info.pc = BL32_BASE, 118 .ep_info.pc = PRELOADED_BL33_BASE, 124 .ep_info.pc = PLAT_RPI3_NS_IMAGE_OFFSET,
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/tf-a-ffa_el3_spmc/plat/socionext/uniphier/ |
A D | uniphier_image_desc.c | 48 .ep_info.pc = UNIPHIER_BL31_OFFSET, 70 .ep_info.pc = UNIPHIER_BL32_OFFSET, 88 .ep_info.pc = UNIPHIER_BL33_OFFSET, 108 uniphier_image_descs[i].ep_info.pc += mem_base; in REGISTER_BL_IMAGE_DESCS()
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/tf-a-ffa_el3_spmc/services/spd/tlkd/ |
A D | tlkd_common.c | 82 uint64_t pc, in tlkd_init_tlk_ep_state() argument 90 assert(pc); in tlkd_init_tlk_ep_state() 111 tlk_entry_point->pc = pc; in tlkd_init_tlk_ep_state()
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/tf-a-ffa_el3_spmc/plat/imx/imx7/common/ |
A D | imx7_bl2_mem_params_desc.c | 20 .ep_info.pc = BL32_BASE, 63 .ep_info.pc = PRELOADED_BL33_BASE, 69 .ep_info.pc = BL33_BASE,
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/tf-a-ffa_el3_spmc/plat/arm/common/aarch32/ |
A D | arm_bl2_mem_params_desc.c | 45 .ep_info.pc = BL32_BASE, 72 .ep_info.pc = PRELOADED_BL33_BASE, 77 .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
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/tf-a-ffa_el3_spmc/plat/intel/soc/common/ |
A D | bl2_plat_mem_params_desc.c | 47 .ep_info.pc = EL3_PAYLOAD_BASE, 67 .ep_info.pc = BL31_BASE, 84 .ep_info.pc = PLAT_NS_IMAGE_OFFSET,
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/tf-a-ffa_el3_spmc/plat/layerscape/common/ |
A D | ls_bl31_setup.c | 53 if (next_image_info->pc) in bl31_plat_get_next_image_ep_info() 87 bl32_image_ep_info.pc = BL32_BASE; in ls_bl31_early_platform_setup() 100 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); in ls_bl31_early_platform_setup() 140 if (bl33_image_ep_info.pc == 0) in ls_bl31_early_platform_setup()
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/tf-a-ffa_el3_spmc/plat/arm/board/diphda/common/ |
A D | diphda_bl2_mem_params_desc.c | 28 .ep_info.pc = BL31_BASE, 46 .ep_info.pc = BL32_BASE, 74 .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
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/tf-a-ffa_el3_spmc/include/common/ |
A D | ep_info.h | 41 __builtin_offsetof(entry_point_info_t, pc), \ 56 __builtin_offsetof(entry_point_info_t, pc), \
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