1 /* 2 * Copyright (c) 2019, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef HANDOFF_H 8 #define HANDOFF_H 9 10 #define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ 11 #define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ 12 #define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ 13 #define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ 14 #define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ 15 #define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ 16 #define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ 17 18 #include <socfpga_plat_def.h> 19 20 typedef struct handoff_t { 21 /* header */ 22 uint32_t header_magic; 23 uint32_t header_device; 24 uint32_t _pad_0x08_0x10[2]; 25 26 /* pinmux configuration - select */ 27 uint32_t pinmux_sel_magic; 28 uint32_t pinmux_sel_length; 29 uint32_t _pad_0x18_0x20[2]; 30 uint32_t pinmux_sel_array[96]; /* offset, value */ 31 32 /* pinmux configuration - io control */ 33 uint32_t pinmux_io_magic; 34 uint32_t pinmux_io_length; 35 uint32_t _pad_0x1a8_0x1b0[2]; 36 uint32_t pinmux_io_array[96]; /* offset, value */ 37 38 /* pinmux configuration - use fpga switch */ 39 uint32_t pinmux_fpga_magic; 40 uint32_t pinmux_fpga_length; 41 uint32_t _pad_0x338_0x340[2]; 42 uint32_t pinmux_fpga_array[42]; /* offset, value */ 43 uint32_t _pad_0x3e8_0x3f0[2]; 44 45 /* pinmux configuration - io delay */ 46 uint32_t pinmux_delay_magic; 47 uint32_t pinmux_delay_length; 48 uint32_t _pad_0x3f8_0x400[2]; 49 uint32_t pinmux_iodelay_array[96]; /* offset, value */ 50 51 /* clock configuration */ 52 53 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 54 uint32_t clock_magic; 55 uint32_t clock_length; 56 uint32_t _pad_0x588_0x590[2]; 57 uint32_t main_pll_mpuclk; 58 uint32_t main_pll_nocclk; 59 uint32_t main_pll_cntr2clk; 60 uint32_t main_pll_cntr3clk; 61 uint32_t main_pll_cntr4clk; 62 uint32_t main_pll_cntr5clk; 63 uint32_t main_pll_cntr6clk; 64 uint32_t main_pll_cntr7clk; 65 uint32_t main_pll_cntr8clk; 66 uint32_t main_pll_cntr9clk; 67 uint32_t main_pll_nocdiv; 68 uint32_t main_pll_pllglob; 69 uint32_t main_pll_fdbck; 70 uint32_t main_pll_pllc0; 71 uint32_t main_pll_pllc1; 72 uint32_t _pad_0x5cc_0x5d0[1]; 73 uint32_t per_pll_cntr2clk; 74 uint32_t per_pll_cntr3clk; 75 uint32_t per_pll_cntr4clk; 76 uint32_t per_pll_cntr5clk; 77 uint32_t per_pll_cntr6clk; 78 uint32_t per_pll_cntr7clk; 79 uint32_t per_pll_cntr8clk; 80 uint32_t per_pll_cntr9clk; 81 uint32_t per_pll_emacctl; 82 uint32_t per_pll_gpiodiv; 83 uint32_t per_pll_pllglob; 84 uint32_t per_pll_fdbck; 85 uint32_t per_pll_pllc0; 86 uint32_t per_pll_pllc1; 87 uint32_t hps_osc_clk_h; 88 uint32_t fpga_clk_hz; 89 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX 90 uint32_t clock_magic; 91 uint32_t clock_length; 92 uint32_t _pad_0x588_0x590[2]; 93 uint32_t main_pll_mpuclk; 94 uint32_t main_pll_nocclk; 95 uint32_t main_pll_nocdiv; 96 uint32_t main_pll_pllglob; 97 uint32_t main_pll_fdbck; 98 uint32_t main_pll_pllc0; 99 uint32_t main_pll_pllc1; 100 uint32_t main_pll_pllc2; 101 uint32_t main_pll_pllc3; 102 uint32_t main_pll_pllm; 103 uint32_t per_pll_emacctl; 104 uint32_t per_pll_gpiodiv; 105 uint32_t per_pll_pllglob; 106 uint32_t per_pll_fdbck; 107 uint32_t per_pll_pllc0; 108 uint32_t per_pll_pllc1; 109 uint32_t per_pll_pllc2; 110 uint32_t per_pll_pllc3; 111 uint32_t per_pll_pllm; 112 uint32_t alt_emacactr; 113 uint32_t alt_emacbctr; 114 uint32_t alt_emacptpctr; 115 uint32_t alt_gpiodbctr; 116 uint32_t alt_sdmmcctr; 117 uint32_t alt_s2fuser0ctr; 118 uint32_t alt_s2fuser1ctr; 119 uint32_t alt_psirefctr; 120 uint32_t hps_osc_clk_h; 121 uint32_t fpga_clk_hz; 122 uint32_t _pad_0x604_0x610[3]; 123 #endif 124 /* misc configuration */ 125 uint32_t misc_magic; 126 uint32_t misc_length; 127 uint32_t _pad_0x618_0x620[2]; 128 } handoff; 129 130 int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); 131 int socfpga_get_handoff(handoff *hoff_ptr); 132 133 #endif 134 135 136