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Searched refs:read_midr (Results 1 – 14 of 14) sorted by relevance

/tf-a-ffa_el3_spmc/lib/cpus/aarch64/
A Dcpuamu.c24 midr = (unsigned int)read_midr(); in midr_match()
/tf-a-ffa_el3_spmc/lib/el3_runtime/aarch32/
A Dcontext_mgmt.c256 write_vpidr(read_midr()); in cm_prepare_el3_exit()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dmce.c116 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in mce_get_curr_cpu_ari_base()
136 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & in mce_get_curr_cpu_ops()
A Dnvg.c207 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in nvg_online_core()
A Dari.c330 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in ari_online_core()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/
A Dplat_psci_handlers.c378 impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in tegra_soc_pwr_domain_on_finish()
438 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; in tegra_soc_pwr_domain_off()
A Dplat_setup.c204 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; in plat_early_platform_setup()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/
A Dtegra_bl31_setup.c188 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) in bl31_early_platform_setup2()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/
A Dhikey_bl2_setup.c227 midr = read_midr(); in hikey_boardid_init()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/drivers/flowctrl/
A Dflowctrl.c166 read_midr() == CORTEX_A53_MIDR); in tegra_fc_cluster_powerdn()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/
A Dplat_psci_handlers.c468 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; in tegra_soc_pwr_domain_off()
/tf-a-ffa_el3_spmc/include/arch/aarch64/
A Darch_helpers.h587 #define read_midr() read_midr_el1() macro
/tf-a-ffa_el3_spmc/plat/renesas/rzg/
A Dbl2_plat_setup.c708 reg = read_midr(); in bl2_el3_early_platform_setup()
/tf-a-ffa_el3_spmc/plat/renesas/rcar/
A Dbl2_plat_setup.c844 reg = read_midr(); in bl2_el3_early_platform_setup()

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