Home
last modified time | relevance | path

Searched refs:reg (Results 1 – 25 of 177) sorted by relevance

12345678

/tf-a-ffa_el3_spmc/drivers/renesas/rcar/pfc/
A Dpfc_init.c43 reg); \
50 reg); \
56 uint32_t reg; in rcar_pfc_init() local
84 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
92 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
109 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
116 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
123 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
130 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
137 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rzg/pfc/
A Dpfc_init.c34 reg); \
41 reg); \
47 uint32_t reg; in rzg_pfc_init() local
65 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
73 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
80 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
87 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
94 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
100 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
107 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rcar/qos/
A Dqos_init.c77 uint32_t reg; in rcar_qos_init() local
118 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
136 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
148 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
161 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
173 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
185 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
189 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
198 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
205 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rzg/qos/
A Dqos_init.c61 uint32_t reg; in rzg_qos_init() local
92 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
104 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
116 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
128 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
132 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
141 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
148 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
155 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
162 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
[all …]
/tf-a-ffa_el3_spmc/plat/imx/common/sci/
A Dimx8_mu.c13 uint32_t reg, i; in MU_Resume() local
15 reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_Resume()
19 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_Resume()
30 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); in MU_EnableRxFullInt()
31 reg |= MU_CR_RIE0_MASK1 >> index; in MU_EnableRxFullInt()
32 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableRxFullInt()
40 reg |= MU_CR_GIE0_MASK1 >> index; in MU_EnableGeneralInt()
41 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableGeneralInt()
66 uint32_t reg; in MU_Init() local
68 reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_Init()
[all …]
/tf-a-ffa_el3_spmc/drivers/marvell/secure_dfx_access/
A Darmada_thermal.c64 uint32_t reg; in armada_ap806_thermal_read() local
66 reg = mmio_read_32(TSEN_STATUS); in armada_ap806_thermal_read()
68 reg = ((reg & TSEN_STATUS_TEMP_OUT_MASK) >> in armada_ap806_thermal_read()
90 uint32_t reg; in armada_ap806_thermal_overheat_irq_init() local
102 reg |= DFX_SERVER_IRQ_EN; in armada_ap806_thermal_overheat_irq_init()
106 reg = mmio_read_32(TSEN_CTRL1); in armada_ap806_thermal_overheat_irq_init()
107 reg |= TSEN_CTRL1_INT_EN; in armada_ap806_thermal_overheat_irq_init()
108 mmio_write_32(TSEN_CTRL1, reg); in armada_ap806_thermal_overheat_irq_init()
198 uint32_t reg; in armada_ap806_thermal_init() local
201 reg &= ~TSEN_CTRL0_RESET; in armada_ap806_thermal_init()
[all …]
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/common/
A Dplat_thermal.c45 uint32_t reg, timeout = 0; in ext_tsen_probe() local
57 reg = mmio_read_32((uintptr_t)&base->ext_tsen_ctrl_lsb); in ext_tsen_probe()
63 reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); in ext_tsen_probe()
67 reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); in ext_tsen_probe()
71 if ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0) { in ext_tsen_probe()
85 uint32_t reg; in ext_tsen_read() local
94 reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); in ext_tsen_read()
95 reg = ((reg & THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK) >> in ext_tsen_read()
103 if (reg >= THERMAL_SEN_OUTPUT_MSB) in ext_tsen_read()
104 reg -= THERMAL_SEN_OUTPUT_COMP; in ext_tsen_read()
[all …]
/tf-a-ffa_el3_spmc/drivers/allwinner/axp/
A Dcommon.c36 ret = axp_read(reg); in axp_clrsetbits()
42 return axp_write(reg, val); in axp_clrsetbits()
77 const struct axp_regulator *reg) in setup_regulator() argument
83 if (mvolt < reg->min_volt || mvolt > reg->max_volt) in setup_regulator()
86 val = (mvolt / reg->step) - (reg->min_volt / reg->step); in setup_regulator()
87 if (val > reg->split) in setup_regulator()
88 val = ((val - reg->split) / 2) + reg->split; in setup_regulator()
90 axp_write(reg->volt_reg, val); in setup_regulator()
91 axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); in setup_regulator()
174 const struct axp_regulator *reg; in axp_setup_regulators() local
[all …]
/tf-a-ffa_el3_spmc/drivers/allwinner/
A Dsunxi_rsb.c39 uint32_t reg, tries = MAX_TRIES; in rsb_wait_bit() local
42 reg = mmio_read_32(SUNXI_R_RSB_BASE + offset); in rsb_wait_bit()
44 if (reg & mask) { in rsb_wait_bit()
54 uint32_t reg; in rsb_wait_stat() local
61 if (reg == 0x01) in rsb_wait_stat()
64 ERROR("%s: 0x%x\n", desc, reg); in rsb_wait_stat()
65 return -reg; in rsb_wait_stat()
113 uint32_t reg; in rsb_set_bus_speed() local
118 reg = source_freq / bus_freq; in rsb_set_bus_speed()
119 if (reg < 2) in rsb_set_bus_speed()
[all …]
/tf-a-ffa_el3_spmc/plat/intel/soc/common/drivers/ccu/
A Dncore_ccu.h70 #define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\ argument
71 + (reg))
72 #define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\ argument
73 + (reg))
74 #define NCORE_CCU_CAI(reg) (NCORE_CCU_REG(NCORE_CAIU_OFFSET)\ argument
75 + (reg))
77 #define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ argument
79 #define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\ argument
82 #define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\ argument
83 + (reg))
/tf-a-ffa_el3_spmc/drivers/renesas/rcar/cpld/
A Dulcb_cpld.c36 uint32_t reg; in gpio_set_value() local
38 reg = mmio_read_32(addr); in gpio_set_value()
40 reg |= (1 << gpio); in gpio_set_value()
42 reg &= ~(1 << gpio); in gpio_set_value()
43 mmio_write_32(addr, reg); in gpio_set_value()
48 uint32_t reg; in gpio_direction_output() local
50 reg = mmio_read_32(addr); in gpio_direction_output()
51 reg |= (1 << gpio); in gpio_direction_output()
52 mmio_write_32(addr, reg); in gpio_direction_output()
57 uint32_t reg; in gpio_pfc() local
[all …]
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/
A Dhisi_pwrc.c42 unsigned int reg = 0; in hisi_pwrc_set_cluster_wfi() local
45 reg = mmio_read_32(ACPU_SC_SNOOP_PWD); in hisi_pwrc_set_cluster_wfi()
46 reg |= PD_DETECT_START0; in hisi_pwrc_set_cluster_wfi()
47 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); in hisi_pwrc_set_cluster_wfi()
49 reg = mmio_read_32(ACPU_SC_SNOOP_PWD); in hisi_pwrc_set_cluster_wfi()
50 reg |= PD_DETECT_START1; in hisi_pwrc_set_cluster_wfi()
51 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); in hisi_pwrc_set_cluster_wfi()
72 unsigned int reg, sec_entrypoint; in hisi_pwrc_setup() local
93 reg = mmio_read_32(AO_SC_SYS_CTRL1); in hisi_pwrc_setup()
95 reg |= AO_SC_SYS_CTRL1_REMAP_SRAM_AARM | in hisi_pwrc_setup()
[all …]
/tf-a-ffa_el3_spmc/plat/layerscape/common/
A Dls_tzc380.c21 unsigned int reg; in tzc380_set_region() local
28 reg = (reg_base + TZASC_REGION_ATTR_OFFSET); in tzc380_set_region()
29 mmio_write_32((uintptr_t)reg, ((security & 0xF) << 28)); in tzc380_set_region()
31 reg = reg_base + TZASC_REGION_LOWADDR_OFFSET; in tzc380_set_region()
32 mmio_write_32((uintptr_t)reg, in tzc380_set_region()
35 reg = reg_base + TZASC_REGION_HIGHADDR_OFFSET; in tzc380_set_region()
36 mmio_write_32((uintptr_t)reg, high_addr); in tzc380_set_region()
38 reg = reg_base + TZASC_REGION_ATTR_OFFSET; in tzc380_set_region()
42 mmio_write_32((uintptr_t)reg, attr_value); in tzc380_set_region()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/timer/
A Dmt_timer.c15 unsigned int reg; in enable_systimer_compensation() local
17 reg = mmio_read_32(CNTCR_REG); in enable_systimer_compensation()
18 reg &= ~COMP_15_EN; in enable_systimer_compensation()
19 reg |= COMP_20_EN; in enable_systimer_compensation()
20 mmio_write_32(CNTCR_REG, reg); in enable_systimer_compensation()
/tf-a-ffa_el3_spmc/include/drivers/allwinner/
A Daxp.h42 int axp_read(uint8_t reg);
43 int axp_write(uint8_t reg, uint8_t val);
44 int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask);
45 #define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) argument
46 #define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask) argument
/tf-a-ffa_el3_spmc/drivers/renesas/common/rpc/
A Drpc_driver.c32 uint32_t product, cut, reg, phy_strtim; in rpc_setup() local
45 reg = mmio_read_32(RPC_PHYCNT); in rpc_setup()
46 reg &= ~RPC_PHYCNT_STRTIM; in rpc_setup()
47 reg |= phy_strtim; in rpc_setup()
48 mmio_write_32(RPC_PHYCNT, reg); in rpc_setup()
49 reg |= RPC_PHYCNT_CAL; in rpc_setup()
50 mmio_write_32(RPC_PHYCNT, reg); in rpc_setup()
/tf-a-ffa_el3_spmc/drivers/arm/css/sds/
A Dsds_private.h67 uint32_t reg[2]; member
71 ((((struct_header_t *)(_header))->reg[0]) & SDS_HEADER_ID_MASK)
73 (((((struct_header_t *)(_header))->reg[0]) >> SDS_HEADER_MINOR_VERSION_SHIFT)\
76 (((((struct_header_t *)(_header))->reg[1]) >> SDS_HEADER_STRUCT_SIZE_SHIFT)\
79 ((((struct_header_t *)(_header))->reg[1]) & SDS_HEADER_VALID_MASK)
85 uint32_t reg[2]; member
89 (((((region_desc_t *)(region))->reg[0]) & SDS_REGION_SIGNATURE_MASK) == SDS_REGION_SIGNATURE)
91 (((((region_desc_t *)(region))->reg[0]) >> SDS_REGION_STRUCT_COUNT_SHIFT)\
94 (((((region_desc_t *)(region))->reg[0]) >> SDS_REGION_SCH_MINOR_SHIFT)\
96 #define GET_SDS_REGION_SIZE(region) ((((region_desc_t *)(region))->reg[1]))
/tf-a-ffa_el3_spmc/drivers/marvell/mochi/
A Dapn806_setup.c129 uint32_t reg; in setup_smmu() local
132 reg = mmio_read_32(SMMU_sACR); in setup_smmu()
133 reg |= SMMU_sACR_PG_64K; in setup_smmu()
134 mmio_write_32(SMMU_sACR, reg); in setup_smmu()
139 uint32_t reg; in init_aurora2() local
142 reg = mmio_read_32(CCU_GSPMU_CR); in init_aurora2()
143 reg |= GSPMU_CPU_CONTROL; in init_aurora2()
154 reg = mmio_read_32(CCU_HTC_CR); in init_aurora2()
156 mmio_write_32(CCU_HTC_CR, reg); in init_aurora2()
243 uint32_t reg; in misc_soc_configurations() local
[all …]
A Dap807_setup.c134 uint32_t reg; in setup_smmu() local
137 reg = mmio_read_32(SMMU_sACR); in setup_smmu()
138 reg |= SMMU_sACR_PG_64K; in setup_smmu()
139 mmio_write_32(SMMU_sACR, reg); in setup_smmu()
144 uint32_t reg; in init_aurora2() local
147 reg = mmio_read_32(CCU_GSPMU_CR); in init_aurora2()
148 reg |= GSPMU_CPU_CONTROL; in init_aurora2()
159 reg = mmio_read_32(CCU_HTC_CR); in init_aurora2()
161 mmio_write_32(CCU_HTC_CR, reg); in init_aurora2()
242 uint32_t reg; in misc_soc_configurations() local
[all …]
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a80x0_mcbin/board/
A Dmarvell_plat_config.c33 uint32_t reg; in marvell_gpio_config() local
35 reg = mmio_read_32(MPP_CONTROL_REGISTER); in marvell_gpio_config()
36 reg |= MPP_CONTROL_MPP_SEL_52_MASK; in marvell_gpio_config()
37 mmio_write_32(MPP_CONTROL_REGISTER, reg); in marvell_gpio_config()
39 reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER); in marvell_gpio_config()
40 reg |= GPIO52_MASK; in marvell_gpio_config()
41 mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg); in marvell_gpio_config()
43 reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER); in marvell_gpio_config()
44 reg &= ~GPIO52_MASK; in marvell_gpio_config()
45 mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg); in marvell_gpio_config()
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a80x0_puzzle/board/
A Dmarvell_plat_config.c33 uint32_t reg; in marvell_gpio_config() local
35 reg = mmio_read_32(MPP_CONTROL_REGISTER); in marvell_gpio_config()
36 reg |= MPP_CONTROL_MPP_SEL_52_MASK; in marvell_gpio_config()
37 mmio_write_32(MPP_CONTROL_REGISTER, reg); in marvell_gpio_config()
39 reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER); in marvell_gpio_config()
40 reg |= GPIO52_MASK; in marvell_gpio_config()
41 mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg); in marvell_gpio_config()
43 reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER); in marvell_gpio_config()
44 reg &= ~GPIO52_MASK; in marvell_gpio_config()
45 mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg); in marvell_gpio_config()
/tf-a-ffa_el3_spmc/drivers/marvell/
A Dap807_clocks_init.c73 unsigned int reg; in aro_to_pll() local
78 reg = mmio_read_32(AP807_CPU_ARO_CTRL(i)); in aro_to_pll()
79 reg |= AP807_CPU_ARO_SEL_PLL_MASK; in aro_to_pll()
80 mmio_write_32(AP807_CPU_ARO_CTRL(i), reg); in aro_to_pll()
85 reg = mmio_read_32(AP807_CPU_ARO_CTRL(i)); in aro_to_pll()
86 reg |= (AP807_CPU_ARO_CLK_EN_MASK); in aro_to_pll()
87 mmio_write_32(AP807_CPU_ARO_CTRL(i), reg); in aro_to_pll()
/tf-a-ffa_el3_spmc/drivers/nxp/dcfg/
A Ddcfg.c38 uint32_t reg; in get_soc_info() local
44 reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SVR_OFFSET); in get_soc_info()
46 soc_info.svr_reg.val = reg; in get_soc_info()
50 (((reg & SVR_SEC_MASK) >> SVR_SEC_SHIFT) == 0) ? true : false; in get_soc_info()
70 uint32_t reg; in get_devdisr5_info() local
75 reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET); in get_devdisr5_info()
78 devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1; in get_devdisr5_info()
79 devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1; in get_devdisr5_info()
80 devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1; in get_devdisr5_info()
82 devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1; in get_devdisr5_info()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rcar/pfc/M3N/
A Dpfc_init_m3n.c935 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7) in pfc_init_m3n()
945 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3) in pfc_init_m3n()
955 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7) in pfc_init_m3n()
965 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7) in pfc_init_m3n()
975 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3) in pfc_init_m3n()
985 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3) in pfc_init_m3n()
995 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7) in pfc_init_m3n()
1015 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7) in pfc_init_m3n()
1025 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3) in pfc_init_m3n()
1041 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3) in pfc_init_m3n()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rzg/pfc/G2H/
A Dpfc_init_g2h.c959 reg = (reg & DRVCTRL0_MASK) | in pfc_init_g2h()
971 reg = (reg & DRVCTRL1_MASK) | in pfc_init_g2h()
983 reg = (reg & DRVCTRL2_MASK) | in pfc_init_g2h()
995 reg = (reg & DRVCTRL3_MASK) | in pfc_init_g2h()
1007 reg = (reg & DRVCTRL4_MASK) | in pfc_init_g2h()
1019 reg = (reg & DRVCTRL5_MASK) | in pfc_init_g2h()
1031 reg = (reg & DRVCTRL6_MASK) | in pfc_init_g2h()
1043 reg = (reg & DRVCTRL7_MASK) | in pfc_init_g2h()
1055 reg = (reg & DRVCTRL8_MASK) | in pfc_init_g2h()
1067 reg = (reg & DRVCTRL9_MASK) | in pfc_init_g2h()
[all …]

Completed in 53 milliseconds

12345678