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Searched refs:reg_base (Results 1 – 25 of 30) sorted by relevance

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/tf-a-ffa_el3_spmc/drivers/rpi3/sdhost/
A Drpi3_sdhost.c50 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_waitcommand() local
73 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in send_command_raw() local
137 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_drain_fifo() local
178 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_print_regs() local
215 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_reset() local
248 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_initialize() local
260 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_send_cmd() local
395 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_set_clock() local
427 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_set_ios() local
454 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_prepare() local
[all …]
/tf-a-ffa_el3_spmc/drivers/imx/usdhc/
A Dimx_usdhc.c44 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_set_clk() local
68 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_initialize() local
82 mmio_write_32(reg_base + MMCBOOT, 0); in imx_usdhc_initialize()
83 mmio_write_32(reg_base + MIXCTRL, 0); in imx_usdhc_initialize()
87 mmio_write_32(reg_base + DLLCTRL, 0); in imx_usdhc_initialize()
112 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_send_cmd() local
130 mmio_write_32(reg_base + INTSIGEN, 0); in imx_usdhc_send_cmd()
254 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_set_ios() local
270 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_prepare() local
272 mmio_write_32(reg_base + DSADDR, buf); in imx_usdhc_prepare()
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A Dimx_usdhc.h13 uintptr_t reg_base; member
/tf-a-ffa_el3_spmc/plat/layerscape/common/
A Dls_tzc380.c22 unsigned int reg_base; in tzc380_set_region() local
25 reg_base = (tzasc_base + TZASC_REGIONS_REG + (region_id << 4)); in tzc380_set_region()
28 reg = (reg_base + TZASC_REGION_ATTR_OFFSET); in tzc380_set_region()
31 reg = reg_base + TZASC_REGION_LOWADDR_OFFSET; in tzc380_set_region()
35 reg = reg_base + TZASC_REGION_HIGHADDR_OFFSET; in tzc380_set_region()
38 reg = reg_base + TZASC_REGION_ATTR_OFFSET; in tzc380_set_region()
/tf-a-ffa_el3_spmc/drivers/rpi3/gpio/
A Drpi3_gpio.c14 static uintptr_t reg_base; variable
48 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_get_select()
73 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_set_select()
109 uintptr_t reg_lev = reg_base + RPI3_GPIO_GPLEV(regN); in rpi3_gpio_get_value()
121 uintptr_t reg_set = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
122 uintptr_t reg_clr = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
138 uintptr_t reg_pud = reg_base + RPI3_GPIO_GPPUD; in rpi3_gpio_set_pull()
139 uintptr_t reg_clk = reg_base + RPI3_GPIO_GPPUDCLK(regN); in rpi3_gpio_set_pull()
161 reg_base = RPI3_GPIO_BASE; in rpi3_gpio_init()
/tf-a-ffa_el3_spmc/plat/socionext/uniphier/
A Duniphier_nand.c52 uintptr_t reg_base; member
88 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 0); in uniphier_nand_block_isbad()
90 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_block_isbad()
103 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_block_isbad()
125 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 1); in uniphier_nand_read_pages()
126 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 1); in uniphier_nand_read_pages()
128 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_read_pages()
148 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_read_pages()
151 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 0); in uniphier_nand_read_pages()
241 nand->reg_base = nand->host_base + 0x100000; in uniphier_nand_hw_init()
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/tf-a-ffa_el3_spmc/drivers/synopsys/emmc/
A Ddw_mmc.c145 mmio_write_32(dw_params.reg_base + DWMMC_CMD, in dw_update_clk()
149 data = mmio_read_32(dw_params.reg_base + DWMMC_CMD); in dw_update_clk()
177 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0); in dw_set_clk()
180 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div); in dw_set_clk()
184 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1); in dw_set_clk()
185 mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0); in dw_set_clk()
194 assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0); in dw_init()
196 base = dw_params.reg_base; in dw_init()
234 base = dw_params.reg_base; in dw_send_cmd()
360 base = dw_params.reg_base; in dw_prepare()
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/tf-a-ffa_el3_spmc/drivers/ufs/
A Dufs.c61 base = ufs_params.reg_base; in ufshc_dme_get()
94 assert((ufs_params.reg_base != 0)); in ufshc_dme_set()
96 base = ufs_params.reg_base; in ufshc_dme_set()
221 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_cmd()
223 mmio_write_32(ufs_params.reg_base + UTRLBAU, in ufs_prepare_cmd()
324 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_query()
604 assert((ufs_params.reg_base != 0) && in ufs_read_capacity()
651 assert((ufs_params.reg_base != 0) && in ufs_read_blocks()
675 assert((ufs_params.reg_base != 0) && in ufs_write_blocks()
741 (params->reg_base != 0) && in ufs_init()
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/tf-a-ffa_el3_spmc/drivers/marvell/comphy/
A Dphy-comphy-3700.c589 uintptr_t reg_base = 0; in mvebu_a3700_comphy_usb3_power_on() local
604 reg_base = COMPHY_INDIRECT_REG; in mvebu_a3700_comphy_usb3_power_on()
608 reg_base = USB3_GBE1_PHY; in mvebu_a3700_comphy_usb3_power_on()
639 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, in mvebu_a3700_comphy_usb3_power_on()
646 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, in mvebu_a3700_comphy_usb3_power_on()
660 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, in mvebu_a3700_comphy_usb3_power_on()
669 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, in mvebu_a3700_comphy_usb3_power_on()
721 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL, in mvebu_a3700_comphy_usb3_power_on()
747 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, in mvebu_a3700_comphy_usb3_power_on()
763 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, in mvebu_a3700_comphy_usb3_power_on()
[all …]
/tf-a-ffa_el3_spmc/drivers/synopsys/ufs/
A Ddw_ufs.c23 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_init()
25 base = params->reg_base; in dwufs_phy_init()
103 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_set_pwr_mode()
105 base = params->reg_base; in dwufs_phy_set_pwr_mode()
196 ufs_params.reg_base = params->reg_base; in dw_ufs_init()
/tf-a-ffa_el3_spmc/drivers/imx/timer/
A Dimx_gpt.h12 void imx_gpt_ops_init(uintptr_t reg_base);
/tf-a-ffa_el3_spmc/include/drivers/synopsys/
A Ddw_mmc.h13 uintptr_t reg_base; member
/tf-a-ffa_el3_spmc/include/drivers/st/
A Dstm32_sdmmc2.h15 uintptr_t reg_base; member
/tf-a-ffa_el3_spmc/plat/intel/soc/common/include/
A Dsocfpga_private.h20 .reg_base = SOCFPGA_MMC_REG_BASE \
/tf-a-ffa_el3_spmc/drivers/st/mmc/
A Dstm32_sdmmc2.c151 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_init()
187 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_send_cmd_req()
418 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_set_ios()
472 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_prepare()
538 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_read()
648 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { in stm32_sdmmc2_dt_get_config()
730 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && in stm32_sdmmc2_mmc_init()
/tf-a-ffa_el3_spmc/include/drivers/
A Ddw_ufs.h102 uintptr_t reg_base; member
/tf-a-ffa_el3_spmc/plat/hisilicon/poplar/include/
A Dhi3798cv200.h75 .reg_base = REG_BASE_MCI, \
/tf-a-ffa_el3_spmc/plat/st/common/
A Dbl2_io_storage.c354 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
357 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
360 params.reg_base = STM32MP_SDMMC3_BASE; in boot_mmc()
365 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
367 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
/tf-a-ffa_el3_spmc/include/drivers/rpi3/sdhost/
A Drpi3_sdhost.h16 uintptr_t reg_base; member
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mm/
A Dimx8mm_bl2_el3_setup.c46 params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE; in imx8mm_usdhc_setup()
/tf-a-ffa_el3_spmc/plat/rpi/rpi3/
A Drpi3_bl2_setup.c35 params.reg_base = RPI3_SDHOST_BASE; in rpi3_sdhost_setup()
/tf-a-ffa_el3_spmc/plat/imx/imx7/warp7/
A Dwarp7_bl2_el3_setup.c106 params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; in warp7_usdhc_setup()
/tf-a-ffa_el3_spmc/plat/imx/imx7/picopi/
A Dpicopi_bl2_el3_setup.c100 params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE; in picopi_usdhc_setup()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/
A Dhikey_bl1_setup.c96 params.reg_base = DWMMC0_BASE; in bl1_platform_setup()
/tf-a-ffa_el3_spmc/drivers/st/spi/
A Dstm32_qspi.c107 uintptr_t reg_base; member
118 return stm32_qspi.reg_base; in qspi_base()
473 &stm32_qspi.reg_base, &size); in stm32_qspi_init()

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