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Searched refs:region (Results 1 – 25 of 40) sorted by relevance

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/tf-a-ffa_el3_spmc/plat/nxp/common/setup/
A Dls_common.c69 + info_dram_regions->region[i].size in mmap_add_ddr_regions_statically()
72 info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
73 info_dram_regions->region[i].size, in mmap_add_ddr_regions_statically()
83 + info_dram_regions->region[i].size in mmap_add_ddr_regions_statically()
89 (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
102 + info_dram_regions->region[i].size in mmap_add_ddr_regions_statically()
105 info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
106 info_dram_regions->region[i].size, in mmap_add_ddr_regions_statically()
125 info_dram_regions->region[i].addr, in mmap_add_ddr_region_dynamically()
126 info_dram_regions->region[i].size, in mmap_add_ddr_region_dynamically()
[all …]
A Dls_bl2_el3_setup.c42 dram_regions_info.region[reg_id].addr = NXP_DRAM0_ADDR; in populate_dram_regions_info()
43 dram_regions_info.region[reg_id].size = in populate_dram_regions_info()
51 dram_remain_size -= dram_regions_info.region[reg_id].size; in populate_dram_regions_info()
55 assert(dram_regions_info.region[reg_id].size > 0); in populate_dram_regions_info()
64 dram_regions_info.region[reg_id].addr = NXP_DRAM1_ADDR; in populate_dram_regions_info()
65 dram_regions_info.region[reg_id].size = in populate_dram_regions_info()
68 dram_remain_size -= dram_regions_info.region[reg_id].size; in populate_dram_regions_info()
74 dram_regions_info.region[reg_id].addr = NXP_DRAM1_ADDR; in populate_dram_regions_info()
75 dram_regions_info.region[reg_id].size = in populate_dram_regions_info()
202 if ((dram_regions_info.region[0].addr == 0) in ls_bl2_el3_plat_arch_setup()
[all …]
A Dls_bl31_setup.c97 dram_regions_info.region[0].addr = 0x80000000; in bl31_early_platform_setup2()
98 dram_regions_info.region[0].size = 0x80000000; in bl31_early_platform_setup2()
99 dram_regions_info.region[1].addr = 0x880000000; in bl31_early_platform_setup2()
100 dram_regions_info.region[1].size = 0x80000000; in bl31_early_platform_setup2()
134 dram_regions_info.region[i].addr = in bl31_early_platform_setup2()
135 loc_dram_regions_info->region[i].addr; in bl31_early_platform_setup2()
136 dram_regions_info.region[i].size = in bl31_early_platform_setup2()
137 loc_dram_regions_info->region[i].size; in bl31_early_platform_setup2()
139 dram_regions_info.region[i].size); in bl31_early_platform_setup2()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/emi_mpu/
A Demi_mpu.c23 unsigned int region; in _emi_mpu_set_protection() local
25 region = (start >> 24) & 0xFF; in _emi_mpu_set_protection()
47 mmio_write_32(EMI_MPU_EA(region), end); in _emi_mpu_set_protection()
57 int region, i; in dump_emi_mpu_regions() local
60 for (region = 0; region < 8; ++region) { in dump_emi_mpu_regions()
66 WARN("region %d:\n", region); in dump_emi_mpu_regions()
81 (region_info->region << 24); in emi_mpu_set_protection()
101 region_info.region = 1; in emi_mpu_init()
112 region_info.region = 2; in emi_mpu_init()
123 region_info.region = 3; in emi_mpu_init()
[all …]
A Demi_mpu.h43 #define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region) * 4) argument
44 #define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region) * 4) argument
47 #define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region) * 4 + \ argument
94 unsigned int region; member
/tf-a-ffa_el3_spmc/drivers/arm/tzc/
A Dtzc380.c32 static void tzc380_write_region_base_low(uintptr_t base, unsigned int region, in tzc380_write_region_base_low() argument
35 mmio_write_32(base + REGION_SETUP_LOW_OFF(region), val); in tzc380_write_region_base_low()
38 static void tzc380_write_region_base_high(uintptr_t base, unsigned int region, in tzc380_write_region_base_high() argument
41 mmio_write_32(base + REGION_SETUP_HIGH_OFF(region), val); in tzc380_write_region_base_high()
44 static void tzc380_write_region_attributes(uintptr_t base, unsigned int region, in tzc380_write_region_attributes() argument
47 mmio_write_32(base + REGION_ATTRIBUTES_OFF(region), val); in tzc380_write_region_attributes()
83 void tzc380_configure_region(uint8_t region, uintptr_t region_base, unsigned int attr) in tzc380_configure_region() argument
87 assert(region < tzc380.num_regions); in tzc380_configure_region()
89 tzc380_write_region_base_low(tzc380.base, region, addr_low(region_base)); in tzc380_configure_region()
90 tzc380_write_region_base_high(tzc380.base, region, addr_high(region_base)); in tzc380_configure_region()
[all …]
A Dtzc400.c240 unsigned int region, in tzc400_configure_region() argument
255 (region < tzc400.num_regions)); in tzc400_configure_region()
269 _tzc400_configure_region(tzc400.base, filters, region, region_base, in tzc400_configure_region()
A Dtzc_dmc500.c32 #define verify_region_attr(region, attr) \ argument
33 ((g_conf_regions[(region)].sec_attr == \
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/
A Dhikey_security.c51 static volatile struct rgn_map_reg *get_rgn_map_reg(uint32_t base, int region, int port) in get_rgn_map_reg() argument
53 uint64_t addr = base + 0x100 + 0x10 * region + 0x400 * (uint64_t)port; in get_rgn_map_reg()
57 static volatile struct rgn_attr_reg *get_rgn_attr_reg(uint32_t base, int region, in get_rgn_attr_reg() argument
60 uint64_t addr = base + 0x104 + 0x10 * region + 0x400 * (uint64_t)port; in get_rgn_attr_reg()
70 int region) in sec_protect() argument
78 assert(region > 0 && region < 16); in sec_protect()
91 rgn_map = get_rgn_map_reg(MDDRC_SECURITY_BASE, region, i); in sec_protect()
92 rgn_attr = get_rgn_attr_reg(MDDRC_SECURITY_BASE, region, i); in sec_protect()
/tf-a-ffa_el3_spmc/drivers/arm/css/sds/
A Dsds_private.h88 #define IS_SDS_REGION_VALID(region) \ argument
89 (((((region_desc_t *)(region))->reg[0]) & SDS_REGION_SIGNATURE_MASK) == SDS_REGION_SIGNATURE)
90 #define GET_SDS_REGION_STRUCTURE_COUNT(region) \ argument
91 (((((region_desc_t *)(region))->reg[0]) >> SDS_REGION_STRUCT_COUNT_SHIFT)\
93 #define GET_SDS_REGION_SCHEMA_VERSION(region) \ argument
94 (((((region_desc_t *)(region))->reg[0]) >> SDS_REGION_SCH_MINOR_SHIFT)\
96 #define GET_SDS_REGION_SIZE(region) ((((region_desc_t *)(region))->reg[1])) argument
/tf-a-ffa_el3_spmc/plat/arm/board/sgi575/fdts/
A Dsgi575_stmm_config.dts89 mem-region@1 {
101 mem-region@2 {
113 mem-region@3 {
125 mem-region@4 {
137 mem-region@5 {
149 mem-region@6 {
158 * Secure Partition Stack region.
160 mem-region@7 {
169 * Firmware config region.
171 mem-region@8 {
[all …]
/tf-a-ffa_el3_spmc/include/drivers/arm/
A Dtzc400.h107 unsigned int region,
131 unsigned int region, in tzc_configure_region() argument
137 tzc400_configure_region(filters, region, region_base, in tzc_configure_region()
A Dtzc380.h138 void tzc380_configure_region(uint8_t region,
147 static inline void tzc_configure_region(uint8_t region, in tzc_configure_region() argument
151 tzc380_configure_region(region, region_base, attr); in tzc_configure_region()
/tf-a-ffa_el3_spmc/docs/components/
A Dffa-manifest-binding.rst160 - Name of the memory region e.g. for debugging purposes.
164 - Count of pages of memory region as a multiple of the translation granule
177 - Base address of the region. The address must be aligned to the translation
183 region of the specified size into the partition's translation regime and
184 then communicate the region properties (including the base address chosen
196 - Name of the device region e.g. for debugging purposes.
203 region.
204 - num-pages: The <u32> number of pages of the region. The total size of
205 the region is this value multiplied by the translation granule size.
245 access and ownership of this device's MMIO region.
A Dxlat-tables-lib-v2-design.rst56 An ``mmap_region`` is an abstract, concise way to represent a memory region to
71 The region attributes specify the type of memory (for example device or cached
75 a User region (EL0) or Privileged region (EL1). See the ``MT_xxx`` definitions
80 the region. For example, assuming the MMU has been configured to use a 4KB
101 The region's granularity is an optional field; if it is not specified the
253 Nonetheless, these APIs will check upfront whether the region can be
256 the new region will overlap another one in an invalid way, or if any other
260 without adding the offending memory region.
348 favour mapping a region using the biggest possible blocks, only creating a
372 order of all regions at all times. As each new region is mapped, existing
[all …]
/tf-a-ffa_el3_spmc/drivers/io/
A Dio_block.c131 io_block_spec_t *region; in block_open() local
137 region = (io_block_spec_t *)spec; in block_open()
139 assert(((region->offset % cur->dev_spec->block_size) == 0) && in block_open()
140 ((region->length % cur->dev_spec->block_size) == 0)); in block_open()
142 cur->base = region->offset; in block_open()
143 cur->size = region->length; in block_open()
A Dio_mtd.c136 io_block_spec_t *region; in mtd_open() local
142 region = (io_block_spec_t *)spec; in mtd_open()
145 cur->base = region->offset; in mtd_open()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/emi_mpu/
A Demi_mpu.c26 int region, in emi_mpu_set_region_protection() argument
50 switch (region) { in emi_mpu_set_region_protection()
A Demi_mpu.h100 int region,
/tf-a-ffa_el3_spmc/plat/nxp/common/sip_svc/
A Dsip_svc.c126 info_dram_regions->region[x1].addr, in nxp_sip_handler()
127 info_dram_regions->region[x1].size); in nxp_sip_handler()
/tf-a-ffa_el3_spmc/docs/plat/
A Dxilinx-versal.rst36 * `VERSAL_ATF_MEM_SIZE`: Specifies the size of the memory region of the bl31 binary.
38 * `VERSAL_BL32_MEM_SIZE`: Specifies the size of the memory region of the bl32 binary.
A Dxilinx-zynqmp.rst35 - ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
37 - ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary.
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/
A Dsoc.c347 if (info_dram_regions->region[dram_idx].size == 0) { in soc_mem_access()
355 info_dram_regions->region[dram_idx].addr, in soc_mem_access()
356 info_dram_regions->region[dram_idx].size, in soc_mem_access()
/tf-a-ffa_el3_spmc/docs/security_advisories/
A Dsecurity-advisory-tfv-3.rst32 Read-Only (RO), non-executable memory region.
35 Any memory region mapped as RO will always be executable, regardless of whether
58 determine whether a region is executable. The Secure EL1&0 translation regime
/tf-a-ffa_el3_spmc/plat/nxp/common/setup/include/
A Dplat_common.h117 region_info_t region[NUM_DRAM_REGIONS]; member

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