Home
last modified time | relevance | path

Searched refs:sc7entry_fw_base (Results 1 – 4 of 4) sorted by relevance

/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A Dplat_setup.c210 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) { in plat_late_platform_setup()
221 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base); in plat_late_platform_setup()
223 sc7entry_end = plat_params->sc7entry_fw_base + in plat_late_platform_setup()
228 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in plat_late_platform_setup()
232 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, in plat_late_platform_setup()
239 ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base, in plat_late_platform_setup()
240 plat_params->sc7entry_fw_base, in plat_late_platform_setup()
286 if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) { in plat_supports_system_suspend()
A Dplat_psci_handlers.c75 if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base) in tegra_soc_validate_power_state()
409 (const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES), in tegra_soc_pwr_domain_power_down_wfi()
489 if (plat_params->sc7entry_fw_base != 0U) { in tegra_soc_pwr_domain_on_finish()
491 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in tegra_soc_pwr_domain_on_finish()
492 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, in tegra_soc_pwr_domain_on_finish()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/
A Dtegra_bl31_setup.c135 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base; in bl31_early_platform_setup2()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/
A Dtegra_private.h49 uint64_t sc7entry_fw_base; member

Completed in 5 milliseconds