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Searched refs:scr (Results 1 – 25 of 26) sorted by relevance

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/tf-a-ffa_el3_spmc/lib/el3_runtime/aarch32/
A Dcontext_mgmt.c57 uint32_t scr, sctlr; in cm_setup_context() local
73 scr = read_scr(); in cm_setup_context()
74 scr &= ~(SCR_NS_BIT | SCR_HCE_BIT); in cm_setup_context()
77 scr |= SCR_NS_BIT; in cm_setup_context()
110 scr |= SCR_HCE_BIT; in cm_setup_context()
117 write_ctx_reg(reg_ctx, CTX_SCR, scr); in cm_setup_context()
177 uint32_t hsctlr, scr; in cm_prepare_el3_exit() local
184 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); in cm_prepare_el3_exit()
185 if ((scr & SCR_HCE_BIT) != 0U) { in cm_prepare_el3_exit()
/tf-a-ffa_el3_spmc/plat/arm/board/arm_fpga/
A Dfpga_pm.c81 u_register_t scr = read_scr_el3(); in fpga_cpu_standby() local
82 write_scr_el3(scr|SCR_IRQ_BIT); in fpga_cpu_standby()
85 write_scr_el3(scr); in fpga_cpu_standby()
/tf-a-ffa_el3_spmc/plat/socionext/synquacer/
A Dsq_psci.c158 u_register_t scr; in sq_cpu_standby() local
162 scr = read_scr_el3(); in sq_cpu_standby()
164 write_scr_el3(scr | SCR_IRQ_BIT); in sq_cpu_standby()
173 write_scr_el3(scr); in sq_cpu_standby()
/tf-a-ffa_el3_spmc/plat/arm/common/aarch64/
A Dexecution_state_switch.c43 u_register_t spsr, pc, scr, sctlr; in arm_execution_state_switch() local
95 scr = read_ctx_reg(el3_ctx, CTX_SCR_EL3); in arm_execution_state_switch()
103 if ((scr & SCR_HCE_BIT) != 0U) in arm_execution_state_switch()
/tf-a-ffa_el3_spmc/plat/ti/k3/common/
A Dk3_psci.c28 u_register_t scr; in k3_cpu_standby() local
30 scr = read_scr_el3(); in k3_cpu_standby()
32 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in k3_cpu_standby()
39 write_scr_el3(scr); in k3_cpu_standby()
/tf-a-ffa_el3_spmc/plat/arm/css/common/
A Dcss_pm.c240 unsigned int scr; in css_cpu_standby() local
244 scr = read_scr_el3(); in css_cpu_standby()
252 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in css_cpu_standby()
261 write_scr_el3(scr); in css_cpu_standby()
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/
A Dbrcm_pm_ops.c194 unsigned int scr; in brcm_cpu_standby() local
198 scr = read_scr_el3(); in brcm_cpu_standby()
206 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in brcm_cpu_standby()
215 write_scr_el3(scr); in brcm_cpu_standby()
/tf-a-ffa_el3_spmc/plat/allwinner/common/
A Dsunxi_scpi_pm.c60 u_register_t scr = read_scr_el3(); in sunxi_cpu_standby() local
64 write_scr_el3(scr | SCR_IRQ_BIT); in sunxi_cpu_standby()
66 write_scr_el3(scr); in sunxi_cpu_standby()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/
A Dhikey960_pm.c42 unsigned long scr; in hikey960_pwr_domain_standby() local
44 scr = read_scr_el3(); in hikey960_pwr_domain_standby()
47 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in hikey960_pwr_domain_standby()
59 write_scr_el3(scr); in hikey960_pwr_domain_standby()
/tf-a-ffa_el3_spmc/plat/rockchip/common/
A Dplat_pm.c185 u_register_t scr; in rockchip_cpu_standby() local
189 scr = read_scr_el3(); in rockchip_cpu_standby()
191 write_scr_el3(scr | SCR_IRQ_BIT); in rockchip_cpu_standby()
200 write_scr_el3(scr); in rockchip_cpu_standby()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/
A Dplat_pm.c183 uint64_t scr; in plat_cpu_standby() local
185 scr = read_scr_el3(); in plat_cpu_standby()
186 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in plat_cpu_standby()
192 write_scr_el3(scr); in plat_cpu_standby()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/
A Dplat_pm.c178 uint64_t scr; in plat_cpu_standby() local
180 scr = read_scr_el3(); in plat_cpu_standby()
181 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in plat_cpu_standby()
187 write_scr_el3(scr); in plat_cpu_standby()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/
A Dplat_pm.c240 u_register_t scr; in plat_cpu_standby() local
242 scr = read_scr_el3(); in plat_cpu_standby()
243 write_scr_el3(scr | SCR_IRQ_BIT); in plat_cpu_standby()
247 write_scr_el3(scr); in plat_cpu_standby()
/tf-a-ffa_el3_spmc/drivers/mmc/
A Dmmc.c32 static unsigned int scr[2]__aligned(16) = { 0 }; variable
166 ret = ops->prepare(0, (uintptr_t)&scr, sizeof(scr)); in mmc_sd_switch()
190 ret = ops->read(0, (uintptr_t)&scr, sizeof(scr)); in mmc_sd_switch()
195 if (((scr[0] & SD_SCR_BUS_WIDTH_4) != 0U) && in mmc_sd_switch()
/tf-a-ffa_el3_spmc/plat/mediatek/common/drivers/uart/
A Duart.c54 mmio_write_32(UART_SCR(base), uart->registers.scr); in mt_uart_restore()
96 uart->registers.scr = mmio_read_32(UART_SCR(base)); in mt_uart_save()
A Duart.h77 uint32_t scr; member
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/
A Dplat_pm.c200 u_register_t scr; in plat_cpu_standby() local
202 scr = read_scr_el3(); in plat_cpu_standby()
203 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in plat_cpu_standby()
209 write_scr_el3(scr); in plat_cpu_standby()
/tf-a-ffa_el3_spmc/lib/psci/
A Dpsci_common.c692 u_register_t scr = read_scr(); in psci_get_ns_ep_info() local
696 write_scr(scr | SCR_NS_BIT); in psci_get_ns_ep_info()
700 sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; in psci_get_ns_ep_info()
703 write_scr(scr); in psci_get_ns_ep_info()
718 mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; in psci_get_ns_ep_info()
/tf-a-ffa_el3_spmc/bl1/aarch32/
A Dbl1_context_mgmt.c80 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); in copy_cpu_ctx_to_smc_ctx()
/tf-a-ffa_el3_spmc/bl32/sp_min/
A Dsp_min_main.c117 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); in copy_cpu_ctx_to_smc_stx()
/tf-a-ffa_el3_spmc/include/arch/aarch32/
A Dsmccc_helpers.h78 u_register_t scr; member
A Darch.h218 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) argument
A Darch_helpers.h226 DEFINE_COPROCR_RW_FUNCS(scr, SCR) in DEFINE_SYSREG_RW_FUNCS()
/tf-a-ffa_el3_spmc/drivers/nxp/sd/
A Dsd_mmc.c762 uint8_t scr[8]; in sd_switch_to_high_freq() local
794 err = esdhc_read_data(mmc, scr, 8U); in sd_switch_to_high_freq()
800 version = scr[0] & U(0xF); in sd_switch_to_high_freq()
/tf-a-ffa_el3_spmc/docs/security_advisories/
A Dsecurity-advisory-tfv-8.rst90 * spsr, lr, sp registers and the `scr` register to the SMC context on entry

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