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/tf-a-ffa_el3_spmc/include/lib/
A Dmmio.h34 uint16_t set) in mmio_clrsetbits_16() argument
36 mmio_write_16(addr, (mmio_read_16(addr) & ~clear) | set); in mmio_clrsetbits_16()
64 static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) in mmio_setbits_32() argument
66 mmio_write_32(addr, mmio_read_32(addr) | set); in mmio_setbits_32()
71 uint32_t set) in mmio_clrsetbits_32() argument
73 mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set); in mmio_clrsetbits_32()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/m0/include/
A Drk3399_mcu.h20 #define mmio_setbits_32(addr, set) \ argument
21 mmio_write_32(addr, (mmio_read_32(addr)) | (set))
22 #define mmio_clrsetbits_32(addr, clear, set) \ argument
23 mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_pmic_wrap.c49 } set[NR_PMIC_WRAP_PHASE]; member
55 .set[PMIC_WRAP_PHASE_ALLINONE] = {
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
154 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_get_cmd()
158 return pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_get_cmd()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/spm/
A Dmt_spm_pmic_wrap.c49 } set[NR_PMIC_WRAP_PHASE]; member
55 .set[PMIC_WRAP_PHASE_ALLINONE] = {
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
154 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_get_cmd()
158 return pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_get_cmd()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/spm/
A Dspm_pmic_wrap.c52 } set[NR_PMIC_WRAP_PHASE]; member
58 .set[PMIC_WRAP_PHASE_ALLINONE] = {
132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
134 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
147 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
150 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
155 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
165 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_get_cmd()
168 return pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_get_cmd()
/tf-a-ffa_el3_spmc/include/drivers/nxp/dcfg/
A Dscfg.h45 #define scfg_clrsetbits32(a, clear, set) \ argument
46 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
52 #define scfg_clrsetbits32(a, clear, set) \ argument
53 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
/tf-a-ffa_el3_spmc/docs/components/spd/
A Dtrusty-dispatcher.rst4 Trusty is a a set of software components, supporting a Trusted Execution
21 If this function is provided ``args->arg0`` must be set to the memory
25 can be set to a platform specific parameter block, and ``args->arg2``
26 should then be set to the size of that block.
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/ptp3/
A Dmtk_ptp3_common.h34 #define ptp3_clrsetbits(addr, clear, set) \ argument
35 mmio_clrsetbits_32((uintptr_t)addr, clear, set)
/tf-a-ffa_el3_spmc/docs/process/
A Dfaq.rst7 Often it is necessary to update your patch set before it is merged. Refer to the
10 If you need to modify an existing patch set with multiple commits, refer to the
18 * How important the patch set is considered by the TF maintainers. Where
20 set and the impact of any delay. Feel free to add a comment to your patch set
23 * The quality of the patch set. Patches are likely to be merged more quickly if
27 * The impact of the patch set. For example, a patch that changes a key generic
63 ``integration`` or another patch set, rather than ``master``. There is a risk
64 that the dependency commits will change (for example due to patch set rework or
78 …et documentation: https://review.trustedfirmware.org/Documentation/intro-user.html#upload-patch-set
/tf-a-ffa_el3_spmc/drivers/imx/usdhc/
A Dimx_usdhc.h133 #define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (… argument
135 #define mmio_setbits32(addr, set) mmio_write_32(addr, mmio_read_32(addr) | (set)) argument
/tf-a-ffa_el3_spmc/plat/socionext/synquacer/drivers/scpi/
A Dsq_scpi.c134 cmd->set = SCPI_SET_NORMAL; in scpi_set_sq_power_state()
160 cmd->set = 0; in scpi_sys_power_state()
189 cmd->set = SCPI_SET_EXTENDED; in scpi_get_draminfo()
A Dsq_scpi.h21 uint32_t set : 1; member
/tf-a-ffa_el3_spmc/docs/perf/
A Dperformance-monitoring-unit.rst79 - If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
91 - If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.
127 - If set to ``1`` enables the cycle counter ``PMCCNTR``.
134 - If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
137 - If set to ``0``, ``PMCCNTR`` will not be affected by this bit and
/tf-a-ffa_el3_spmc/docs/security_advisories/
A Dsecurity-advisory-tfv-5.rst32 bit is set to zero, the cycle counter (when enabled) counts during secure world
36 normal and secure worlds, normal world code can set ``PMCR_EL0.DP`` to zero to
43 some implementations, ``PMCR_EL0.DP`` is set to zero by default. This and other
/tf-a-ffa_el3_spmc/plat/arm/board/rde1edge/fdts/
A Drde1edge_nt_fw_config.dts14 * value of platform-id and config-id will be set to the
/tf-a-ffa_el3_spmc/plat/arm/board/sgi575/fdts/
A Dsgi575_nt_fw_config.dts14 * value of platform-id and config-id will be set to the
/tf-a-ffa_el3_spmc/docs/components/
A Dplatform-interrupt-controller-API.rst117 This API should set the priority of the interrupt specified by first parameter
118 ``id`` to the value set by the second parameter ``priority``.
121 writes to GIC *Priority Register* set interrupt priority.
167 This API should set the interrupt specified by first parameter ``id`` to the
193 - When the build option ``GICV2_G0_FOR_EL3`` is set to ``0`` (the default),
224 This API should set the routing mode of Share Peripheral Interrupt (SPI)
237 writes to the GIC *Target Register* (GICv2) or *Route Register* (GICv3) to set
248 This API should set the interrupt specified by first parameter ``id`` to
253 and writes to the GIC *Set Pending Register* to set the interrupt pending
279 This API should set the priority mask (first parameter) in the interrupt
/tf-a-ffa_el3_spmc/docs/plat/arm/
A Darm-build-options.rst32 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
39 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
40 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
86 of the translation tables library instead of version 2. It is set to 0 by
129 TF-A no longer supports earlier SCP versions. If this option is set to 1
132 - ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
139 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
142 which supports multi-chip operation. If ``CSS_SGI_CHIP_COUNT`` is set to any
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/
A Dsoc.def18 # set to GIC400 or GIC500
21 # set to CCI400 or CCN504 or CCN508
24 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
/tf-a-ffa_el3_spmc/plat/arm/board/rdn1edge/fdts/
A Drdn1edge_nt_fw_config.dts14 * value of platform-id and config-id will be set to the
/tf-a-ffa_el3_spmc/plat/arm/board/rdv1mc/fdts/
A Drdv1mc_nt_fw_config.dts14 * value of platform-id and config-id will be set to the
/tf-a-ffa_el3_spmc/plat/arm/board/rdn2/fdts/
A Drdn2_nt_fw_config.dts14 * value of platform-id and config-id will be set to the
/tf-a-ffa_el3_spmc/plat/arm/board/rdv1/fdts/
A Drdv1_nt_fw_config.dts14 * value of platform-id and config-id will be set to the
/tf-a-ffa_el3_spmc/docs/getting_started/
A Dbuild-options.rst62 is set to '1'.
135 addition to the options set by the build system.
168 ``SPMD_SPM_AT_SEL2`` is set.
454 addition to the one set by the build system.
530 set to 1 as well.
537 set to ``1``.
576 set to ``1``.
666 must also be set to ``1``.
858 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
868 set to '2'.
[all …]
/tf-a-ffa_el3_spmc/plat/brcm/common/
A Dbrcm_scpi.c153 cmd->set = SCPI_SET_NORMAL; in scpi_set_brcm_power_state()
241 cmd->set = 0; in scpi_sys_power_state()

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