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Searched refs:shift (Results 1 – 24 of 24) sorted by relevance

/tf-a-ffa_el3_spmc/drivers/rpi3/gpio/
A Drpi3_gpio.c47 int shift = 3 * (gpio % 10); in rpi3_gpio_get_select() local
51 ret = (sel >> shift) & 0x07; in rpi3_gpio_get_select()
72 int shift = 3 * (gpio % 10); in rpi3_gpio_set_select() local
75 uint32_t mask = U(0x07) << shift; in rpi3_gpio_set_select()
108 int shift = gpio % 32; in rpi3_gpio_get_value() local
112 if ((value >> shift) & 0x01) in rpi3_gpio_get_value()
120 int shift = gpio % 32; in rpi3_gpio_set_value() local
126 mmio_write_32(reg_clr, U(1) << shift); in rpi3_gpio_set_value()
129 mmio_write_32(reg_set, U(1) << shift); in rpi3_gpio_set_value()
137 int shift = gpio % 32; in rpi3_gpio_set_pull() local
[all …]
/tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/pm_service/
A Dpm_api_ioctl.c178 unsigned int val, mask, shift; in pm_ioctl_set_sgmii_mode() local
186 shift = 0; in pm_ioctl_set_sgmii_mode()
189 shift = 1; in pm_ioctl_set_sgmii_mode()
192 shift = 2; in pm_ioctl_set_sgmii_mode()
195 shift = 3; in pm_ioctl_set_sgmii_mode()
283 unsigned int shift; in pm_ioctl_sd_set_tapdelay() local
288 shift = 0; in pm_ioctl_sd_set_tapdelay()
318 shift), 0); in pm_ioctl_sd_set_tapdelay()
323 shift)); in pm_ioctl_sd_set_tapdelay()
328 (value << shift)); in pm_ioctl_sd_set_tapdelay()
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/soc/
A Dsoc.h96 #define regs_update_bit_set(addr, shift) \ argument
97 regs_update_bits((addr), 0x1, 0x1, (shift))
98 #define regs_update_bit_clr(addr, shift) \ argument
99 regs_update_bits((addr), 0x0, 0x1, (shift))
102 uint32_t mask, uint32_t shift);
A Dsoc.c91 uint32_t mask, uint32_t shift) in regs_update_bits() argument
97 tmp = orig & ~(mask << shift); in regs_update_bits()
98 tmp |= (val & mask) << shift; in regs_update_bits()
/tf-a-ffa_el3_spmc/drivers/st/etzpc/
A Detzpc.c97 uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT; in etzpc_configure_decprot() local
103 (uint32_t)ETZPC_DECPROT0_MASK << shift, in etzpc_configure_decprot()
104 masked_decprot << shift); in etzpc_configure_decprot()
115 uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT; in etzpc_get_decprot() local
121 value = (mmio_read_32(base_decprot + ETZPC_DECPROT0) >> shift) & in etzpc_get_decprot()
134 uint32_t shift = BIT(decprot_id % IDS_PER_DECPROT_LOCK_REGS); in etzpc_lock_decprot() local
139 mmio_write_32(base_decprot + ETZPC_DECPROT_LOCK0, shift); in etzpc_lock_decprot()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/soc/
A Dsoc.h131 #define regs_updata_bit_set(addr, shift) \ argument
132 regs_updata_bits((addr), 0x1, 0x1, (shift))
133 #define regs_updata_bit_clr(addr, shift) \ argument
134 regs_updata_bits((addr), 0x0, 0x1, (shift))
137 uint32_t mask, uint32_t shift);
A Dsoc.c111 uint32_t mask, uint32_t shift) in regs_updata_bits() argument
117 tmp = orig & ~(mask << shift); in regs_updata_bits()
118 tmp |= (val & mask) << shift; in regs_updata_bits()
/tf-a-ffa_el3_spmc/plat/rockchip/common/include/
A Dplat_private.h52 #define BITS_SHIFT(bits, shift) (bits << (shift)) argument
56 #define BITS_WITH_WMASK(bits, msk, shift)\ argument
57 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
/tf-a-ffa_el3_spmc/drivers/renesas/common/ddr/
A Ddram_sub_func.c41 uint32_t shift; in rcar_dram_get_boot_status() local
46 shift = GPIO_BKUP_TRG_SHIFT_CONDOR; in rcar_dram_get_boot_status()
49 shift = GPIO_BKUP_TRG_SHIFT_EBISU; in rcar_dram_get_boot_status()
52 shift = GPIO_BKUP_TRG_SHIFT_SALVATOR; in rcar_dram_get_boot_status()
57 if (reg_data & BIT(shift)) in rcar_dram_get_boot_status()
/tf-a-ffa_el3_spmc/plat/socionext/uniphier/
A Duniphier_soc_info.c16 unsigned int shift) in uniphier_get_revision_field() argument
25 return (mmio_read_32(reg) >> shift) & mask; in uniphier_get_revision_field()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/spm/
A Dspm_mcdi.c410 unsigned int pwr_status, shift, i, flag = 0; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off() local
419 shift = i + PCM_MCDI_CA72_PWRSTA_SHIFT; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
420 flag |= (pwr_status & (1 << shift)) >> shift; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
429 shift = i + PCM_MCDI_CA53_PWRSTA_SHIFT; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
430 flag |= (pwr_status & (1 << shift)) >> shift; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
/tf-a-ffa_el3_spmc/plat/mediatek/common/drivers/rtc/
A Drtc_mt6359p.c13 uint16_t mask, uint16_t shift) in RTC_Config_Interface() argument
19 pmic_reg &= ~(mask << shift); in RTC_Config_Interface()
20 pmic_reg |= (data << shift); in RTC_Config_Interface()
/tf-a-ffa_el3_spmc/drivers/brcm/
A Diproc_gpio.c58 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in gpio_set_bit() local
63 val |= BIT(shift); in gpio_set_bit()
65 val &= ~BIT(shift); in gpio_set_bit()
73 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in gpio_get_bit() local
75 return !!(mmio_read_32(base + offset) & BIT(shift)); in gpio_get_bit()
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/soc/
A Dsoc.h13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) argument
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/
A Dsoc.h21 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) argument
/tf-a-ffa_el3_spmc/drivers/nxp/ddr/nxp-ddr/
A Dddrc.c63 uint32_t map, shift, highest; in bist() local
83 shift = (3U - i % 4U) * 8U + 2U; in bist()
84 map = (temp32 >> shift) & U(0x3F); in bist()
93 shift = (3U - pos % 4U) * 8U + 2U; in bist()
95 pos >> 2U, shift, map_save); in bist()
96 temp32 = map_save & ~(U(0x3F) << shift); in bist()
97 temp32 |= 8U << shift; in bist()
/tf-a-ffa_el3_spmc/lib/aarch32/
A Dcache_helpers.S84 .macro dcsw_op shift, fw, ls
86 ubfx r3, r2, \shift, \fw
/tf-a-ffa_el3_spmc/lib/aarch64/
A Dcache_helpers.S82 .macro dcsw_op shift, fw, ls
84 ubfx x3, x9, \shift, \fw
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/common/
A Dplat_pm.c504 unsigned int shift; in plat_marvell_power_off_gpio() local
549 shift = pm_cfg->cfg.gpio.info[gpio].gpio_index % 32; in plat_marvell_power_off_gpio()
551 reg &= ~(1 << shift); in plat_marvell_power_off_gpio()
553 reg |= (1 << shift); in plat_marvell_power_off_gpio()
/tf-a-ffa_el3_spmc/include/arch/aarch64/
A Darch_helpers.h575 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; in el_implemented() local
577 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; in el_implemented()
/tf-a-ffa_el3_spmc/drivers/nxp/ddr/phy-gen2/
A Dphy.c2290 int shift = read ? 4 : 0; in parse_odt() local
2298 odt[i] |= (1 << i) << shift; in parse_odt()
2308 odt[j] |= (1 << i) << shift; in parse_odt()
2320 odt[j] |= (1 << i) << shift; in parse_odt()
2329 odt[j] |= (1 << i) << shift; in parse_odt()
2338 odt[j] |= (1 << i) << shift; in parse_odt()
2351 odt[j] |= (1 << i) << shift; in parse_odt()
/tf-a-ffa_el3_spmc/docs/components/
A Dromlib-design.rst122 This will have for effect to shift down all the BL images by 1 page.
/tf-a-ffa_el3_spmc/drivers/marvell/comphy/
A Dphy-comphy-cp110.c252 uint32_t shift = COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; in mvebu_cp110_comphy_set_pipe_selector() local
254 uint32_t mask = COMMON_SELECTOR_COMPHY_MASK << shift; in mvebu_cp110_comphy_set_pipe_selector()
297 (pipe_sel << shift)); in mvebu_cp110_comphy_set_pipe_selector()
/tf-a-ffa_el3_spmc/docs/
A Dchange-log.rst487 - Added helper to calculate the position shift from MPIDR
1191 - Fixed runtime instability caused by incorrect CPUID shift value
1716 - imx: Fix shift-overflow errors, the rdc memory region slot's offset,
2089 - Enable -Wshift-overflow=2 to check for undefined shift behavior

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