| /tf-a-ffa_el3_spmc/docs/plat/ |
| A D | imx8.rst | 13 and 1 Cortex-M4 system controller.
15 The i.MX8QX is with 4 Cortex-A35 ARM core and 1 Cortex-M4 system
19 control for system-level resources on i.MX8. The heart of the system
20 controller is a Cortex-M4 that executes system controller firmware.
54 with certain offset for BOOT ROM. The system controller firmware,
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| A D | qemu-sbsa.rst | 7 is made by EDK2 build system by composing BL1 and FIP. Second parameter for Qemu
9 contains of UEFI and EFI variables (also made by EDK2 build system). Semihosting
50 EDK2 build system, refer to edk2-platform repo for full build instructions.
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| A D | synquacer.rst | 38 few specialist tools. On a Debian or Ubuntu operating system try:
103 - Providing your Developerbox is fully working and has on operating system
104 installed then you can adopt your the newly compiled system firmware using
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| /tf-a-ffa_el3_spmc/plat/arm/board/rde1edge/fdts/ |
| A D | rde1edge_nt_fw_config.dts | 13 * Place holder for system-id node with default values. The
17 system-id {
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| /tf-a-ffa_el3_spmc/plat/arm/board/sgi575/fdts/ |
| A D | sgi575_nt_fw_config.dts | 13 * Place holder for system-id node with default values. The
17 system-id {
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| /tf-a-ffa_el3_spmc/plat/arm/board/rdn1edge/fdts/ |
| A D | rdn1edge_nt_fw_config.dts | 13 * Place holder for system-id node with default values. The
17 system-id {
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| /tf-a-ffa_el3_spmc/plat/arm/board/rdv1mc/fdts/ |
| A D | rdv1mc_nt_fw_config.dts | 13 * Place holder for system-id node with default values. The
17 system-id {
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| /tf-a-ffa_el3_spmc/plat/arm/board/rdn2/fdts/ |
| A D | rdn2_nt_fw_config.dts | 13 * Place holder for system-id node with default values. The
17 system-id {
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| /tf-a-ffa_el3_spmc/plat/arm/board/rdv1/fdts/ |
| A D | rdv1_nt_fw_config.dts | 13 * Place holder for system-id node with default values. The
17 system-id {
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| A D | nvg.c | 62 uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask) in nvg_update_cstate_info() argument
79 if (system != 0U) { in nvg_update_cstate_info()
80 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | in nvg_update_cstate_info()
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| A D | mce.c | 124 nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system, in mce_update_cstate_info()
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| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | alt-boot-flows.rst | 7 On a pre-production system, the ability to execute arbitrary, bare-metal code at
13 configuration required to put the system in the expected state.
21 - putting the system into a known architectural state;
30 The system is left in the same state as when entering BL31 in the default boot
61 connection is usually available in a pre-production system. The user is free to
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| A D | nvg.c | 48 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, in nvg_update_cstate_info() argument
68 if (system != 0U) { in nvg_update_cstate_info()
69 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | in nvg_update_cstate_info()
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| A D | ari.c | 161 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, in ari_update_cstate_info() argument
182 if (system != 0U) { in ari_update_cstate_info()
183 val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | in ari_update_cstate_info()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/drivers/ |
| A D | mce.h | 57 uint32_t system; member
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| /tf-a-ffa_el3_spmc/docs/threat_model/ |
| A D | index.rst | 5 that helps us identify potential threats and mitigations affecting a system.
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/drivers/include/ |
| A D | mce_private.h | 50 uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/include/ |
| A D | mce_private.h | 98 uint32_t system,
224 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
247 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
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| /tf-a-ffa_el3_spmc/drivers/nxp/ddr/nxp-ddr/ |
| A D | README.odt | 3 Two-slot system
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt6795/ |
| A D | plat_pm.c | 50 struct system_context *system, in system_cluster() argument
53 return &system->cluster[clusterid]; in system_cluster()
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| /tf-a-ffa_el3_spmc/docs/about/ |
| A D | features.rst | 31 - |PSCI| library support for CPU, cluster and system power management
81 secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
118 - Ongoing support for new Arm system architecture specifications.
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| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | platform-interrupt-controller-API.rst | 34 associated to system-wide peripherals, and these interrupts can target any PE in
35 the system.
87 ``id``. PEs in the system are expected to receive only enabled interrupts.
102 ``id``. PEs in the system are not expected to receive disabled interrupts.
231 system. The ``mpidr`` parameter is ignored in this case.
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| A D | ras.rst | 52 RAS nodes are components in the system capable of signalling errors to PEs
57 architecture allows for error records to be accessible via system or
64 - For memory-mapped error record, its base address and size in KB; for a system
84 And, for system register ones:
173 orderly shutdown of the system, as recovery may be impossible.
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/ |
| A D | plat_psci_handlers.c | 147 cstate_info.system = (uint32_t)TEGRA_ARI_SYSTEM_SC7; in tegra_soc_pwr_domain_suspend()
428 cstate_info.system = (uint32_t)TEGRA_ARI_SYSTEM_SC1; in tegra_soc_pwr_domain_on_finish()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8173/ |
| A D | plat_pm.c | 93 struct system_context *system, in system_cluster() argument
96 return &system->cluster[clusterid]; in system_cluster()
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