| /tf-a-ffa_el3_spmc/include/arch/aarch32/ |
| A D | asm_macros.S | 219 .macro softudiv div:req,top:req,bot:req,temp:req
222 cmp \temp, \top, lsr #1
225 cmp \temp, \top, lsr #1
230 cmp \top, \temp
231 subcs \top, \top,\temp
|
| /tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/secure/ |
| A D | secure.h | 35 #define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) argument
|
| /tf-a-ffa_el3_spmc/plat/rockchip/common/drivers/parameter/ |
| A D | ddr_parameter.c | 53 uint64_t base, top; in ddr_region_usage_parse() local
77 top = base + mmio_read_64(addr + size_offset); in ddr_region_usage_parse()
83 p.ns_top[i] = RG_SIZE_MB(top); in ddr_region_usage_parse()
|
| /tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/ |
| A D | soc.h | 102 #define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) argument
|
| /tf-a-ffa_el3_spmc/drivers/renesas/common/emmc/ |
| A D | emmc_utility.c | 79 uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom) in emmc_bit_field() argument
83 uint32_t index_top = (uint32_t) (15 - (top >> 3)); in emmc_bit_field()
104 value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1)); in emmc_bit_field()
|
| A D | emmc_def.h | 51 uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom);
|
| /tf-a-ffa_el3_spmc/fdts/ |
| A D | n1sdp-single-chip.dts | 23 * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
|
| /tf-a-ffa_el3_spmc/docs/perf/ |
| A D | performance-monitoring-unit.rst | 120 - The effects of ``PMEVTYPER<n>`` are applied on top of this.
145 - The effects of ``PMCNTENSET`` and ``PMCR.DP`` are applied on top of this.
|
| /tf-a-ffa_el3_spmc/docs/plat/ |
| A D | warp7.rst | 50 The following commands assume that a directory exits in the top-level TFA build
159 arm-trusted-firmware top-level directory.
187 # Copy signed BL2 to top-level directory
|
| A D | xilinx-zynqmp.rst | 73 common to the cluster are grouped in the power domain on the top.
|
| A D | qemu-sbsa.rst | 42 Need to copy them into top directory for EDK2 compilation.
|
| A D | poplar.rst | 9 of running any commercial set-top solution based on Linux or Android.
|
| /tf-a-ffa_el3_spmc/docs/getting_started/ |
| A D | docs-build.rst | 76 top-level Makefile for |TF-A| itself.
|
| A D | psci-lib-integration-guide.rst | 252 This function is the top level handler for SMCs which fall within the
278 mentioned at top of this section. This function must be called with Data cache
|
| A D | build-options.rst | 417 bottom, higher addresses at the top. This build flag can be set to '1' to
418 invert this behavior. Lower addresses will be printed at the top and higher
|
| A D | porting-guide.rst | 2861 are received from the top-level exception handler.
3027 other drivers. For example, file-system drivers may be implemented on top of
|
| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | exception-handling.rst | 143 top-level handler for interrupts that target EL3, as described in the
187 to use the top *n* of the 7 remaining bits to identify and assign interrupts
199 that at least ``n+1`` top bits of GIC priority are writeable.
279 The parameters are as obtained from the top-level :ref:`EL3 interrupt handler
535 #. The |EHF|, during its initialisation, registers a top-level interrupt handler
542 #. The top-level EL3 interrupt handler executes. The handler acknowledges the
|
| A D | ras.rst | 113 ``cookie``, and ``handle`` parameters from the :ref:`top-level exception handler
207 top-level RAS exception handler. ``ras_ea_handler`` is responsible for iterating
|
| A D | romlib-design.rst | 121 On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM.
|
| A D | sdei.rst | 337 To work this around, it's advised that the top-level event handlers are
|
| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 869 top of Hafnium in S-EL2
892 - The top-level Makefile now supports building FipTool on Windows
3991 DDR-DRAM memory at 0x80000000 excluding the top 16MB. The top 16MB is
3994 - BL3-2 can now reside in the top 16MB of DRAM which is accessible only to
4011 the BL3-1/BL3-2 NOBITS sections on top of them has been added to the
4014 - The top 16MB of the 2GB DDR-DRAM memory at 0x80000000 is configured
4103 overlaying the BL3-1/BL3-2 NOBITS sections on top of these at runtime.
4189 - Removed the concept of top/bottom image loading. The image loader now
|
| /tf-a-ffa_el3_spmc/docs/process/ |
| A D | coding-guidelines.rst | 30 ``.checkpatch.conf`` file in the top-level directory.
|
| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | firmware-design.rst | 137 to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
1698 data are relocated to the top of Trusted SRAM at runtime.
1703 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
1716 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
|