| /tf-a-ffa_el3_spmc/plat/arm/css/sgm/ |
| A D | sgm_topology.c | 16 return get_plat_config()->topology->power_tree; in plat_get_power_domain_tree_desc()
25 return get_plat_config()->topology->plat_cluster_core_count; in plat_arm_get_cluster_core_count()
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| A D | sgm_plat_config.c | 46 .topology = &sgm775_topology
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/ |
| A D | fvp_topology.c | 43 cluster_count = FCONF_GET_PROPERTY(hw_config, topology, plat_cluster_count); in plat_get_power_domain_tree_desc()
44 cpus_per_cluster = FCONF_GET_PROPERTY(hw_config, topology, cluster_cpu_count); in plat_get_power_domain_tree_desc()
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| /tf-a-ffa_el3_spmc/plat/arm/css/sgm/include/ |
| A D | sgm_plat_config.h | 37 const css_topology_t *topology; member
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| /tf-a-ffa_el3_spmc/plat/qemu/common/sp_min/ |
| A D | sp_min-qemu.mk | 10 plat/qemu/topology.c
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| /tf-a-ffa_el3_spmc/lib/psci/ |
| A D | psci_setup.c | 124 *topology) in populate_power_domain_tree()
153 num_children = topology[parent_node_index]; in populate_power_domain_tree()
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| /tf-a-ffa_el3_spmc/docs/components/fconf/ |
| A D | index.rst | 46 captures the hardware topology of the platform from the HW_CONFIG device tree.
57 such as topology, GIC controller, PSCI hooks, CPU ID etc.
71 FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/fconf/ |
| A D | fconf_hw_config_getter.c | 294 FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
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| /tf-a-ffa_el3_spmc/fdts/ |
| A D | arm_fpga.dts | 7 * topology is auto-detected by BL31, and the /cpus node is created and
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| A D | fvp-defs.dtsi | 10 /* Set default topology values if not passed from platform's makefile */
27 /* Get platform's topology */
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| A D | fvp-defs-dynamiq.dtsi | 10 /* Set default topology values if not passed from platform's makefile */
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| /tf-a-ffa_el3_spmc/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 22 As the number and topology layout of the CPU cores differs significantly
47 fill the CPU topology nodes. It will also be passed on to BL33, by
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| /tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/pm_service/ |
| A D | pm_api_clock.h | 301 uint32_t *topology);
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| A D | pm_api_clock.c | 2478 uint32_t *topology) in pm_api_clock_get_topology() argument
2492 memset(topology, 0, CLK_TOPOLOGY_PAYLOAD_LEN); in pm_api_clock_get_topology()
2503 topology[i] = clock_nodes[index + i].type; in pm_api_clock_get_topology()
2504 topology[i] |= clock_nodes[index + i].clkflags << in pm_api_clock_get_topology()
2507 topology[i] |= (typeflags & CLK_TYPEFLAGS_BITS_MASK) << in pm_api_clock_get_topology()
2509 topology[i] |= (typeflags & CLK_TYPEFLAGS2_BITS_MASK) >> in pm_api_clock_get_topology()
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| A D | pm_api_sys.c | 838 uint32_t *topology) in pm_clock_get_topology() argument
840 return pm_api_clock_get_topology(clock_id, index, topology); in pm_clock_get_topology()
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| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | psci-pd-tree.rst | 10 system. This approach is inflexible because a change to the topology
23 mechanism used to populate the power domain topology tree.
73 The following example power domain topology tree will be used to describe the
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| A D | firmware-design.rst | 570 - Detect the system topology.
577 As part of the PSCI initializations, BL31 detects the system topology. It also
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| /tf-a-ffa_el3_spmc/plat/qemu/qemu/ |
| A D | platform.mk | 174 ${PLAT_QEMU_COMMON_PATH}/topology.c \
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| /tf-a-ffa_el3_spmc/plat/brcm/board/stingray/ |
| A D | platform.mk | 199 plat/${SOC_DIR}/src/topology.c \
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| /tf-a-ffa_el3_spmc/docs/plat/marvell/armada/ |
| A D | porting.rst | 83 This file defines the dram topology and parameters of the target board.
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| A D | build.rst | 180 The DDR topology map index/name, default is 0.
299 the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
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| /tf-a-ffa_el3_spmc/docs/getting_started/ |
| A D | porting-guide.rst | 136 Defines the total number of nodes in the power domain topology
139 data structures to represent power domain topology.
821 This function plays a crucial role in the power domain topology framework in
836 be invoked by BL31 after the power domain topology is initialized and can
838 represents the power domain topology and how this relates to the linear CPU
2121 example, the system). More details on the power domain topology and its
2233 topology tree description. The format and method to construct this array are
2236 statically or dynamically, to initialize the power domain topology tree. In case
2238 plat_my_core_pos() should also be implemented suitably so that the topology tree
2240 form the platform interface for the PSCI topology framework.
[all …]
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| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | secure-partition-manager.rst | 406 - *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping.
475 Platform topology
553 started using EC[N] on PE[N] (see `Platform topology`_). If the partition is a
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| /tf-a-ffa_el3_spmc/docs/plat/arm/fvp/ |
| A D | index.rst | 112 build the topology tree within TF-A. By default TF-A is configured for dual
113 cluster topology and this option can be used to override the default value.
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| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 493 - Added support for topology handling
711 - Added support for detecting topology at runtime
1142 - Fixed initialization issues caused by incorrect MPIDR topology mapping
1556 the stack size for bl1 and bl2, remove re-definition of topology related
1565 topology information to board folder
1699 for RESET_TO_BL31=1, topology description of cpus for DynamIQ based
1706 - arm/rde1edge: Fix incorrect topology tree description
3660 - Enhanced topology description support to allow multi-cluster topology
3835 hierarchical arrangement of cores) and of power domain topology, instead
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