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Searched refs:uint64_t (Results 1 – 25 of 482) sorted by relevance

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/tf-a-ffa_el3_spmc/plat/qti/qtiseclib/inc/
A Dqtiseclib_defs.h43 uint64_t x0;
44 uint64_t x1;
45 uint64_t x2;
46 uint64_t x3;
47 uint64_t x4;
48 uint64_t x5;
49 uint64_t x6;
50 uint64_t x7;
51 uint64_t x8;
52 uint64_t x9;
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/tf-a-ffa_el3_spmc/bl32/tsp/
A Dtsp_private.h67 uint64_t arg1,
68 uint64_t arg2,
69 uint64_t arg3,
70 uint64_t arg4,
71 uint64_t arg5,
72 uint64_t arg6,
73 uint64_t arg7);
75 uint64_t arg1,
115 uint64_t arg1, uint64_t arg2,
116 uint64_t arg3, uint64_t arg4,
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A Dtsp_main.c72 uint64_t arg1, uint64_t arg2, in tsp_smc()
73 uint64_t arg3, uint64_t arg4, in tsp_smc()
74 uint64_t arg5, uint64_t arg6) in tsp_smc()
105 uint64_t arg1, in set_smc_args()
106 uint64_t arg2, in set_smc_args()
107 uint64_t arg3, in set_smc_args()
108 uint64_t arg4, in set_smc_args()
109 uint64_t arg5, in set_smc_args()
110 uint64_t arg6, in set_smc_args()
111 uint64_t arg7) in set_smc_args()
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/tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/pm_service/
A Dpm_svc_main.c261 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, in pm_smc_handler()
262 uint64_t x4, void *cookie, void *handle, uint64_t flags) in pm_smc_handler()
293 uint64_t address = (uint64_t)pm_arg[2] << 32; in pm_smc_handler()
365 (uint64_t)buff[1] | ((uint64_t)buff[2] << 32)); in pm_smc_handler()
404 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
416 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
439 (uint64_t)result[0] | ((uint64_t)result[1] << 32), in pm_smc_handler()
440 (uint64_t)result[2] | ((uint64_t)result[3] << 32)); in pm_smc_handler()
491 (uint64_t)data[2] | ((uint64_t)data[3] << 32)); in pm_smc_handler()
617 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32)); in pm_smc_handler()
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A Dpm_svc_main.h13 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
14 uint64_t x4, void *cookie, void *handle,
15 uint64_t flags);
17 uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
18 uint64_t x4, void *cookie, void *handle,
19 uint64_t flags);
/tf-a-ffa_el3_spmc/plat/xilinx/versal/pm_service/
A Dpm_svc_main.c132 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, in pm_smc_handler()
133 uint64_t x4, void *cookie, void *handle, uint64_t flags) in pm_smc_handler()
219 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buff[0] << 32), in pm_smc_handler()
220 (uint64_t)buff[1] | ((uint64_t)buff[2] << 32)); in pm_smc_handler()
247 (uint64_t)result[0] | ((uint64_t)result[1] << 32), in pm_smc_handler()
248 (uint64_t)result[2] | ((uint64_t)result[3] << 32)); in pm_smc_handler()
264 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
278 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
292 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
303 (uint64_t)data[1] | ((uint64_t)data[2] << 32)); in pm_smc_handler()
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A Dpm_svc_main.h13 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
14 uint64_t x4, void *cookie, void *handle,
15 uint64_t flags);
/tf-a-ffa_el3_spmc/services/std_svc/spm/common/include/
A Dspm_partition.h26 uint64_t mpidr;
33 uint64_t sp_mem_base;
34 uint64_t sp_mem_limit;
35 uint64_t sp_image_base;
36 uint64_t sp_stack_base;
37 uint64_t sp_heap_base;
39 uint64_t sp_shared_buf_base;
40 uint64_t sp_image_size;
41 uint64_t sp_pcpu_stack_size;
42 uint64_t sp_heap_size;
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/tf-a-ffa_el3_spmc/include/services/
A Dspmd_svc.h15 uint64_t spmd_smc_handler(uint32_t smc_fid,
16 uint64_t x1,
17 uint64_t x2,
18 uint64_t x3,
19 uint64_t x4,
22 uint64_t flags);
28 uint64_t x1,
29 uint64_t x2,
30 uint64_t x3,
31 uint64_t x4,
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/tf-a-ffa_el3_spmc/plat/mediatek/common/
A Dmtk_plat_common.h42 uint64_t pc;
43 uint64_t r0;
44 uint64_t r1;
45 uint64_t r2;
46 uint64_t k32_64;
50 uint64_t bootarg_loc;
51 uint64_t bootarg_size;
52 uint64_t bl33_start_addr;
53 uint64_t tee_info_addr;
74 void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4);
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/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/drivers/mce/
A Dnvg.c29 uint64_t nvg_get_version(void) in nvg_get_version()
33 return (uint64_t)nvg_get_result(); in nvg_get_version()
45 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); in nvg_set_wake_time()
64 uint64_t val = 0; in nvg_update_cstate_info()
127 (uint64_t)core & MCE_CORE_ID_MASK); in nvg_online_core()
149 (uint64_t)gsc_idx); in nvg_update_ccplex_gsc()
182 uint64_t val = 0ULL; in nvg_enter_cstate()
212 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | in nvg_enable_strict_checking_mode()
220 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | in nvg_verify_strict_checking_mode()
237 (uint64_t)TEGRA_NVG_REBOOT); in nvg_system_reboot()
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/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/dp/
A Dcdn_dp.c27 static uint64_t *hdcp_key_pdata;
32 uint64_t dp_hdcp_ctrl(uint64_t type) in dp_hdcp_ctrl()
37 hdcp_key_pdata = (uint64_t *)&key; in dp_hdcp_ctrl()
40 if (hdcp_key_pdata == (uint64_t *)(&key + 1)) in dp_hdcp_ctrl()
50 uint64_t dp_hdcp_store_key(uint64_t x1, in dp_hdcp_store_key()
51 uint64_t x2, in dp_hdcp_store_key()
52 uint64_t x3, in dp_hdcp_store_key()
53 uint64_t x4, in dp_hdcp_store_key()
54 uint64_t x5, in dp_hdcp_store_key()
55 uint64_t x6) in dp_hdcp_store_key()
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A Dcdn_dp.h40 uint64_t dp_hdcp_ctrl(uint64_t type);
42 uint64_t dp_hdcp_store_key(uint64_t x1,
43 uint64_t x2,
44 uint64_t x3,
45 uint64_t x4,
46 uint64_t x5,
47 uint64_t x6);
/tf-a-ffa_el3_spmc/services/std_svc/spm/common/
A Dlogical_mm_sp.c61 uint64_t comm_size, uint64_t core_pos) in spmc_sp_call()
63 uint64_t rc; in spmc_sp_call()
104 uint64_t rc; in spmc_mm_interface_handler()
142 static uint64_t direct_req_secure_smc_handler(uint64_t x1, uint64_t x2, in direct_req_secure_smc_handler()
143 uint64_t x3, uint64_t x4, in direct_req_secure_smc_handler()
147 uint64_t rc; in direct_req_secure_smc_handler()
215 static uint64_t direct_req_non_secure_smc_handler(uint64_t x1, in direct_req_non_secure_smc_handler()
216 uint64_t x2, in direct_req_non_secure_smc_handler()
217 uint64_t x3, in direct_req_non_secure_smc_handler()
249 static uint64_t handle_ffa_direct_request(uint32_t smc_fid, bool secure_origin, uint64_t x1, uint6… in handle_ffa_direct_request()
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/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dnvg.c22 uint64_t val = 0ULL; in nvg_enter_cstate()
37 write_actlr_el1(val | (uint64_t)state); in nvg_enter_cstate()
51 uint64_t val = 0ULL; in nvg_update_cstate_info()
107 (uint64_t)type), (uint64_t)time); in nvg_update_crossover_time()
115 uint64_t ret; in nvg_read_cstate_stats()
130 (uint64_t)state)); in nvg_read_cstate_stats()
139 uint64_t val; in nvg_write_cstate_stats()
158 (uint64_t)state), val); in nvg_write_cstate_stats()
175 uint64_t val; in nvg_is_sc7_allowed()
226 ((uint64_t)core & MCE_CORE_ID_MASK)); in nvg_online_core()
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/tf-a-ffa_el3_spmc/include/lib/extensions/
A Damu_private.h12 uint64_t amu_group0_cnt_read_internal(unsigned int idx);
13 void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val);
15 uint64_t amu_group1_cnt_read_internal(unsigned int idx);
16 void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val);
20 uint64_t amu_group0_voffset_read_internal(unsigned int idx);
21 void amu_group0_voffset_write_internal(unsigned int idx, uint64_t val);
23 uint64_t amu_group1_voffset_read_internal(unsigned int idx);
24 void amu_group1_voffset_write_internal(unsigned int idx, uint64_t val);
A Damu.h69 uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
72 uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1];
76 uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
78 uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS];
91 uint64_t amu_group0_cnt_read(unsigned int idx);
92 void amu_group0_cnt_write(unsigned int idx, uint64_t val);
95 uint64_t amu_group0_voffset_read(unsigned int idx);
96 void amu_group0_voffset_write(unsigned int idx, uint64_t val);
103 uint64_t amu_group1_cnt_read(unsigned int idx);
104 void amu_group1_cnt_write(unsigned int idx, uint64_t val);
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/tf-a-ffa_el3_spmc/plat/arm/common/aarch64/
A Darm_pauth.c19 uint64_t return_addr = (uint64_t)__builtin_return_address(0U); in plat_init_apkey()
20 uint64_t frame_addr = (uint64_t)__builtin_frame_address(0U); in plat_init_apkey()
21 uint64_t cntpct = read_cntpct_el0(); in plat_init_apkey()
24 uint64_t key_lo = (return_addr << 13) ^ frame_addr ^ cntpct; in plat_init_apkey()
25 uint64_t key_hi = (frame_addr << 15) ^ return_addr ^ cntpct; in plat_init_apkey()
/tf-a-ffa_el3_spmc/services/std_svc/spm/spmc/
A Dspmc_shared_mem.h39 uint64_t address;
61 uint64_t reserved_8_15;
213 uint64_t handle;
214 uint64_t tag;
235 uint64_t handle;
250 uint64_t flags);
260 uint64_t flags);
280 uint64_t flags);
291 uint64_t flags);
298 uint64_t x4,
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/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/crypt/
A Dcrypt.h12 uint64_t crypt_set_hdcp_key_ex(uint64_t x1, uint64_t x2, uint64_t x3);
13 uint64_t crypt_set_hdcp_key_num(uint32_t num);
14 uint64_t crypt_clear_hdcp_key(void);
/tf-a-ffa_el3_spmc/plat/rockchip/common/drivers/parameter/
A Dddr_parameter.h31 uint64_t boundary;
34 uint64_t ns_base[DDR_REGION_NR_MAX];
35 uint64_t ns_top[DDR_REGION_NR_MAX];
38 uint64_t s_base[DDR_REGION_NR_MAX + 1];
39 uint64_t s_top[DDR_REGION_NR_MAX + 1];
42 struct param_ddr_usage ddr_region_usage_parse(uint64_t addr, uint64_t max_mb);
/tf-a-ffa_el3_spmc/plat/mediatek/common/drivers/timer/
A Dmt_timer.c13 uint64_t normal_time_base;
14 uint64_t atf_time_base;
16 void sched_clock_init(uint64_t normal_base, uint64_t atf_base) in sched_clock_init()
22 uint64_t sched_clock(void) in sched_clock()
24 uint64_t cval; in sched_clock()
25 uint64_t rel_base; in sched_clock()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/drivers/include/
A Dmce_private.h47 uint64_t nvg_get_version(void);
51 int32_t nvg_set_cstate_stat_query_value(uint64_t data);
52 uint64_t nvg_get_cstate_stat_query_value(void);
65 void nvg_set_request_data(uint64_t req, uint64_t data);
66 void nvg_set_request(uint64_t req);
67 uint64_t nvg_get_result(void);
68 uint64_t nvg_cache_clean(void);
69 uint64_t nvg_cache_clean_inval(void);
70 uint64_t nvg_cache_inval_all(void);
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/
A Dtegra_private.h37 uint64_t tzdram_size;
39 uint64_t tzdram_base;
45 uint64_t boot_profiler_shmem_base;
47 uint64_t sc7entry_fw_size;
49 uint64_t sc7entry_fw_base;
128 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
145 uint64_t x1,
146 uint64_t x2,
147 uint64_t x3,
148 uint64_t x4,
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/tf-a-ffa_el3_spmc/services/spd/tlkd/
A Dtlkd_private.h103 uint64_t mpidr;
104 uint64_t c_rt_ctx;
111 uint64_t tlkd_va_translate(uintptr_t va, int type);
112 uint64_t tlkd_enter_sp(uint64_t *c_rt_ctx);
113 void __dead2 tlkd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
114 uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx);
116 uint64_t ret);
119 uint64_t pc,

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