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/tf-a-ffa_el3_spmc/include/drivers/arm/cryptocell/712/
A Dutil.h24 #define UTIL_INVERSE_UINT32_BYTES(val) (val) argument
26 #define UTIL_INVERSE_UINT32_BYTES(val) \
27 …(((val) >> 24) | (((val) & 0x00FF0000) >> 8) | (((val) & 0x0000FF00) << 8) | (((val) & 0x000000FF)…
32 #define UTIL_REVERT_UINT32_BYTES(val) \ argument
33 …(((val) >> 24) | (((val) & 0x00FF0000) >> 8) | (((val) & 0x0000FF00) << 8) | (((val) & 0x000000FF)…
35 #define UTIL_REVERT_UINT32_BYTES(val) (val)
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/
A Dpaxc.c118 uint32_t val; in paxc_cfg_link_cap() local
132 uint32_t val; in paxc_cfg_id() local
162 val = 0xff; in paxc_init()
165 val = 0x0; in paxc_init()
169 val); in paxc_init()
222 val |= 0x1; in paxc_mhb_ns_init()
237 val |= 0x1; in paxc_mhb_ns_init()
242 val |= 0x1; in paxc_mhb_ns_init()
247 val |= 0x1; in paxc_mhb_ns_init()
252 val |= 0x1; in paxc_mhb_ns_init()
[all …]
A Dbl31_setup.c79 unsigned int val; in brcm_stingray_dma_pl330_init() local
313 unsigned int val; in brcm_stingray_amac_init() local
393 unsigned int val; in brcm_stingray_smmu_init() local
401 val |= (0x1 << 12); in brcm_stingray_smmu_init()
493 unsigned int val; in brcm_stingray_scr_init() local
535 unsigned int val; in brcm_stingray_hsls_tzpcprot_init() local
541 val = 0; in brcm_stingray_hsls_tzpcprot_init()
542 val |= BIT(6); /* SDIO1 */ in brcm_stingray_hsls_tzpcprot_init()
544 val |= BIT(0); /* AMAC */ in brcm_stingray_hsls_tzpcprot_init()
586 unsigned int val; in brcm_stingray_audio_init() local
[all …]
A Dsdio.c33 unsigned int val; in brcm_stingray_sdio_init() local
41 val = SDIO0_CAP0_CFG; in brcm_stingray_sdio_init()
42 INFO("caps0 0x%x\n", val); in brcm_stingray_sdio_init()
46 val = SDIO0_CAP1_CFG; in brcm_stingray_sdio_init()
47 INFO("caps1 0x%x\n", val); in brcm_stingray_sdio_init()
65 val = mmio_read_32(sdio0_cfg->io_ctrl_base); in brcm_stingray_sdio_init()
68 mmio_write_32(sdio0_cfg->io_ctrl_base, val); in brcm_stingray_sdio_init()
94 val = SDIO1_CAP0_CFG; in brcm_stingray_sdio_init()
95 INFO("caps0 0x%x\n", val); in brcm_stingray_sdio_init()
98 val = SDIO1_CAP1_CFG; in brcm_stingray_sdio_init()
[all …]
A Dpaxb.c350 uint32_t val, timeout; in paxb_start_link_up() local
394 uint32_t val; in pcie_core_pwron_switch() local
520 uint32_t val) in paxb_rc_cfg_write() argument
530 unsigned int val; in paxb_rc_cfg_read() local
537 return val; in paxb_rc_cfg_read()
555 val |= mps; in paxb_cfg_mps()
632 val = val | (nph << NPH_FC_INIT_SHIFT); in paxb_cfg_pdl_ctrl()
633 val = val | (pd << PD_FC_INIT_SHIFT); in paxb_cfg_pdl_ctrl()
638 val = val | (ph << PH_INIT_SHIFT); in paxb_cfg_pdl_ctrl()
769 uint32_t val; in paxb_smmu_cfg() local
[all …]
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/pwm/
A Dpwm.c29 uint32_t i, val; in disable_pwms() local
34 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); in disable_pwms()
35 if (((val >> GRF_GPIO4C2_IOMUX_SHIFT) & in disable_pwms()
43 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); in disable_pwms()
44 if (((val >> GRF_GPIO4C6_IOMUX_SHIFT) & in disable_pwms()
53 if (((val >> PMUGRF_GPIO1C3_IOMUX_SHIFT) & in disable_pwms()
62 if (((val >> PMUGRF_GPIO0A6_IOMUX_SHIFT) & in disable_pwms()
73 val = mmio_read_32(PWM_BASE + PWM_CTRL(i)); in disable_pwms()
74 if ((val & PWM_ENABLE) != PWM_ENABLE) in disable_pwms()
86 uint32_t i, val; in enable_pwms() local
[all …]
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/drivers/smmu/
A Dsmmu.c32 uint32_t val, cb_idx, smmu_id, ctx_base; in tegra_smmu_init() local
38 val |= SMMU_GSR0_PGSIZE_64K; in tegra_smmu_init()
51 val = tegra_smmu_read_32(smmu_id, in tegra_smmu_init()
55 (SMMU_GSR0_PGSIZE_64K * cb_idx), val); in tegra_smmu_init()
75 uint32_t cb_idx, ctx_base, smmu_id, val; in tegra_smmu_verify() local
82 if (0U == (val & SMMU_GSR0_PGSIZE_64K)) { in tegra_smmu_verify()
84 __func__, smmu_id, val); in tegra_smmu_verify()
91 __func__, smmu_id, val); in tegra_smmu_verify()
99 __func__, smmu_id, val); in tegra_smmu_verify()
107 val = tegra_smmu_read_32(smmu_id, in tegra_smmu_verify()
[all …]
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/drivers/pmc/
A Dpmc.c32 uint32_t val; in tegra_pmc_cpu_on() local
37 val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); in tegra_pmc_cpu_on()
44 val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); in tegra_pmc_cpu_on()
45 } while ((val & PMC_TOGGLE_START) != 0U); in tegra_pmc_cpu_on()
51 tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); in tegra_pmc_cpu_on()
59 } while ((val & (1U << 8)) != 0U); in tegra_pmc_cpu_on()
73 uint32_t val; in tegra_pmc_cpu_setup() local
77 val = (uint32_t)(reset_addr >> 32U); in tegra_pmc_cpu_setup()
86 uint32_t val; in tegra_pmc_lock_cpu_vectors() local
90 val |= PMC_SECURE_DISABLE2_WRITE22_ON; in tegra_pmc_lock_cpu_vectors()
[all …]
/tf-a-ffa_el3_spmc/drivers/nxp/gpio/
A Dnxp_gpio.c23 uint32_t val = 0U; in set_gpio_bit() local
39 val = gpio_read32(gpdir); in set_gpio_bit()
40 val = val | bit_num; in set_gpio_bit()
41 gpio_write32(gpdir, val); in set_gpio_bit()
44 val = gpio_read32(gpdat); in set_gpio_bit()
45 val = val | bit_num; in set_gpio_bit()
46 gpio_write32(gpdat, val); in set_gpio_bit()
48 val = gpio_read32(gpdat); in set_gpio_bit()
60 uint32_t val = 0U; in clr_gpio_bit() local
78 val = val & ~(bit_num); in clr_gpio_bit()
[all …]
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/driver/ext_sram_init/
A Dext_sram_init.c181 unsigned int val, tmp; in brcm_stingray_pnor_sram_init() local
203 val |= (0x74); in brcm_stingray_pnor_sram_init()
207 val |= (0x76); in brcm_stingray_pnor_sram_init()
211 val |= (0xff); in brcm_stingray_pnor_sram_init()
228 val = 0x00129A44; in brcm_stingray_pnor_sram_init()
236 val = 0x0; in brcm_stingray_pnor_sram_init()
241 val &= ~(0x3); in brcm_stingray_pnor_sram_init()
242 val |= (0x1); /* set_mw */ in brcm_stingray_pnor_sram_init()
247 val &= ~(0x3); in brcm_stingray_pnor_sram_init()
255 val = 0x1; in brcm_stingray_pnor_sram_init()
[all …]
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/drivers/flowctrl/
A Dflowctrl.c67 uint32_t val; in tegra_fc_prepare_suspend() local
72 tegra_fc_halt_cpu(cpu_id, val); in tegra_fc_prepare_suspend()
76 tegra_fc_cpu_csr(cpu_id, val | csr); in tegra_fc_prepare_suspend()
137 uint32_t val; in tegra_fc_cluster_idle() local
149 tegra_fc_prepare_suspend(cpu, val); in tegra_fc_cluster_idle()
158 uint32_t val; in tegra_fc_cluster_powerdn() local
179 uint32_t val; in tegra_fc_is_ccx_allowed() local
204 uint32_t val; in tegra_fc_soc_powerdn() local
233 uint32_t val; in tegra_fc_cpu_off() local
241 tegra_fc_cpu_csr(cpu, val); in tegra_fc_cpu_off()
[all …]
/tf-a-ffa_el3_spmc/drivers/imx/uart/
A Dimx_uart.c57 mmio_write_32(base + offset, val); in write_reg()
68 uint32_t val; in console_imx_uart_core_init() local
75 } while (!(val & IMX_UART_CR2_SRST)); in console_imx_uart_core_init()
83 write_reg(base_addr, IMX_UART_CR2_OFFSET, val); in console_imx_uart_core_init()
87 write_reg(base_addr, IMX_UART_CR3_OFFSET, val); in console_imx_uart_core_init()
97 val |= IMX_UART_FCR_DCEDTE; in console_imx_uart_core_init()
134 uint32_t val; in console_imx_uart_core_putc() local
145 } while (!(val & IMX_UART_STAT2_TXDC)); in console_imx_uart_core_putc()
160 uint32_t val; in console_imx_uart_core_getc() local
163 if (val & IMX_UART_TS_RXEMPTY) in console_imx_uart_core_getc()
[all …]
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/
A Dhisi_ipc.c40 unsigned int val = 0, cpu_val = 0; in hisi_cpus_pd_in_cluster_besides_curr() local
44 val = val >> (cluster * 16); in hisi_cpus_pd_in_cluster_besides_curr()
61 unsigned int val; in hisi_cpus_powered_off_besides_curr() local
100 unsigned int val = 0; in hisi_ipc_cpu_on_off() local
110 val |= (0x01 << offset); in hisi_ipc_cpu_on_off()
132 unsigned int val = 0; in hisi_ipc_cluster_on_off() local
142 val |= (0x01 << offset); in hisi_ipc_cluster_on_off()
163 unsigned int val = 0; in hisi_ipc_cpu_suspend() local
170 val |= (0x01 << offset); in hisi_ipc_cpu_suspend()
179 unsigned int val; in hisi_ipc_cluster_suspend() local
[all …]
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mq/
A Dgpc.c79 uint32_t val; in imx_set_cluster_powerdown() local
91 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); in imx_set_cluster_powerdown()
92 val &= ~EN_L2_WFI_PDN; in imx_set_cluster_powerdown()
93 val |= L2PGE | EN_PLAT_PDN; in imx_set_cluster_powerdown()
96 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); in imx_set_cluster_powerdown()
110 val &= ~A53_LPM_MASK; /* clear the C0~1 LPM */ in imx_set_cluster_powerdown()
119 val |= EN_L2_WFI_PDN; in imx_set_cluster_powerdown()
120 val &= ~(L2PGE | EN_PLAT_PDN); in imx_set_cluster_powerdown()
128 uint32_t val; in imx_gpc_init() local
149 val |= IRQ_SRC_A53_WUP; in imx_gpc_init()
[all …]
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A Dplat_psci_handlers.c204 uint32_t val; in tegra_soc_pwr_domain_suspend() local
275 uint32_t val, mask; in tegra_reset_all_dma_masters() local
280 val = GPU_RESET_BIT; in tegra_reset_all_dma_masters()
308 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
314 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
321 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
326 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
332 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
337 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
348 uint32_t val; in tegra_soc_pwr_domain_power_down_wfi() local
[all …]
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/drivers/se/
A Dsecurity_engine.c144 uint32_t val = 0; in tegra_se_operation_complete() local
196 if (val != 0U) { in tegra_se_operation_complete()
212 uint32_t val = 0; in tegra_se_operation_prepare() local
243 uint32_t val = 0; in tegra_se_context_save_atomic() local
371 uint32_t val; in tegra_se_generate_srk() local
410 uint32_t val; in tegra_se_lp_generate_random_data() local
508 uint32_t val = 0; in tegra_se_lp_sticky_bits_context_save() local
541 uint32_t val = 0; in tegra_se_aeskeytable_context_save() local
622 uint32_t val = 0; in tegra_se_lp_rsakeytable_context_save() local
758 uint32_t val; in tegra_se_lock() local
[all …]
/tf-a-ffa_el3_spmc/drivers/arm/gic/v2/
A Dgicv2_private.h46 uint8_t val = target & GIC_TARGET_CPU_MASK; in gicd_set_itargetsr() local
48 mmio_write_8(base + GICD_ITARGETSR + id, val); in gicd_set_itargetsr()
51 static inline void gicd_write_sgir(uintptr_t base, unsigned int val) in gicd_write_sgir() argument
53 mmio_write_32(base + GICD_SGIR, val); in gicd_write_sgir()
116 mmio_write_32(base + GICC_CTLR, val); in gicc_write_ctlr()
121 mmio_write_32(base + GICC_PMR, val); in gicc_write_pmr()
126 mmio_write_32(base + GICC_BPR, val); in gicc_write_BPR()
132 mmio_write_32(base + GICC_IAR, val); in gicc_write_IAR()
137 mmio_write_32(base + GICC_EOIR, val); in gicc_write_EOIR()
142 mmio_write_32(base + GICC_HPPIR, val); in gicc_write_hppir()
[all …]
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mm/
A Dgpc.c24 unsigned int val; in imx_gpc_init() local
36 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
38 val |= 0x30c00000; in imx_gpc_init()
40 val &= ~(1 << 6); in imx_gpc_init()
70 val = mmio_read_32(IMX_GPC_BASE + SLPCR); in imx_gpc_init()
71 val &= ~SLPCR_EN_DSM; in imx_gpc_init()
73 val |= SLPCR_A53_FASTWUP_WAIT_MODE; in imx_gpc_init()
75 val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); in imx_gpc_init()
77 val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT); in imx_gpc_init()
78 val |= (0x5 << SLPCR_STBY_COUNT_SHFT); in imx_gpc_init()
[all …]
/tf-a-ffa_el3_spmc/drivers/nxp/csu/
A Dcsu.c19 uint32_t val; in enable_layerscape_ns_access() local
24 val = be32toh(mmio_read_32((uintptr_t)reg)); in enable_layerscape_ns_access()
26 val &= 0x0000ffffU; in enable_layerscape_ns_access()
27 val |= csu_ns_dev[i].val << 16U; in enable_layerscape_ns_access()
29 val &= 0xffff0000U; in enable_layerscape_ns_access()
30 val |= csu_ns_dev[i].val; in enable_layerscape_ns_access()
32 mmio_write_32((uintptr_t)reg, htobe32(val)); in enable_layerscape_ns_access()
/tf-a-ffa_el3_spmc/plat/layerscape/common/
A Dns_access.c20 uint32_t val; in enable_devices_ns_access() local
25 val = be32toh(mmio_read_32((uintptr_t)reg)); in enable_devices_ns_access()
27 val &= 0x0000ffff; in enable_devices_ns_access()
28 val |= _ns_dev[i].val << 16; in enable_devices_ns_access()
30 val &= 0xffff0000; in enable_devices_ns_access()
31 val |= _ns_dev[i].val; in enable_devices_ns_access()
33 mmio_write_32((uintptr_t)reg, htobe32(val)); in enable_devices_ns_access()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/drivers/se/
A Dse.c195 uint32_t val = 0U; in tegra_se_sha256_hash_operation_complete() local
217 if (val != 0U) { in tegra_se_sha256_hash_operation_complete()
219 val); in tegra_se_sha256_hash_operation_complete()
251 if (val > 0U) { in tegra_se_start_normal_operation()
352 val); in tegra_se_calculate_sha256_hash()
402 val); in tegra_se_save_sha256_pmc_scratch()
415 int32_t val = 0; in tegra_se_calculate_save_sha256() local
430 if (val != 0) { in tegra_se_calculate_save_sha256()
432 return val; in tegra_se_calculate_save_sha256()
442 if (val != 0) { in tegra_se_calculate_save_sha256()
[all …]
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mn/
A Dgpc.c26 unsigned int val; in imx_gpc_init() local
38 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
40 val |= CORE_WKUP_FROM_GIC; in imx_gpc_init()
42 val &= ~MASTER0_LPM_HSK; in imx_gpc_init()
72 val = mmio_read_32(IMX_GPC_BASE + SLPCR); in imx_gpc_init()
73 val &= ~SLPCR_EN_DSM; in imx_gpc_init()
75 val |= SLPCR_A53_FASTWUP_WAIT_MODE; in imx_gpc_init()
77 val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); in imx_gpc_init()
79 val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT); in imx_gpc_init()
80 val |= (0x5 << SLPCR_STBY_COUNT_SHFT); in imx_gpc_init()
[all …]
/tf-a-ffa_el3_spmc/lib/libfdt/
A Dfdt_addresses.c17 uint32_t val; in fdt_cells() local
27 val = fdt32_to_cpu(*c); in fdt_cells()
28 if (val > FDT_MAX_NCELLS) in fdt_cells()
31 return (int)val; in fdt_cells()
36 int val; in fdt_address_cells() local
39 if (val == 0) in fdt_address_cells()
41 if (val == -FDT_ERR_NOTFOUND) in fdt_address_cells()
43 return val; in fdt_address_cells()
48 int val; in fdt_size_cells() local
51 if (val == -FDT_ERR_NOTFOUND) in fdt_size_cells()
[all …]
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/drivers/pwrc/
A Dhisi_pwrc.c131 unsigned int val; in hisi_get_cpuidle_flag() local
134 val &= 0xF; in hisi_get_cpuidle_flag()
136 return val; in hisi_get_cpuidle_flag()
168 unsigned int val; in hisi_set_cluster_pwdn_flag() local
186 val = val >> (16 + (cluster << 2)); in hisi_get_cpu_boot_flag()
187 val &= 0xF; in hisi_get_cpu_boot_flag()
190 return val; in hisi_get_cpu_boot_flag()
199 val = val >> (16 + (cluster << 2)); in hisi_test_cpu_down()
200 val &= 0xF; in hisi_test_cpu_down()
203 if (val) in hisi_test_cpu_down()
[all …]
/tf-a-ffa_el3_spmc/drivers/arm/gic/v3/
A Dgicv3_private.h78 #define GICD_WRITE(REG, base, id, val) \ argument
389 unsigned int val) in gicr_write_icenabler() argument
427 unsigned int val) in gicr_write_icfgr() argument
445 unsigned int val) in gicr_write_icpendr() argument
474 unsigned int val) in gicr_write_igroupr() argument
503 unsigned int val) in gicr_write_igrpmodr() argument
519 unsigned int val) in gicr_ipriorityr_write() argument
548 unsigned int val) in gicr_write_isactiver() argument
577 unsigned int val) in gicr_write_isenabler() argument
606 unsigned int val) in gicr_write_ispendr() argument
[all …]

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