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/tf-a-ffa_el3_spmc/lib/compiler-rt/builtins/
A Dpopcountdi2.c22 du_int x2 = (du_int)a; in __popcountdi2() local
23 x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL); in __popcountdi2()
25 x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL); in __popcountdi2()
27 x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL; in __popcountdi2()
29 su_int x = (su_int)(x2 + (x2 >> 32)); in __popcountdi2()
/tf-a-ffa_el3_spmc/plat/nxp/common/aarch64/
A Dbl31_data.S37 clz x2, x0
49 add x2, x2, x1
59 mul x2, x2, x0
73 sub x2, x2, x1
77 dc ivac, x2
97 clz x2, x0
109 add x2, x2, x1
119 mul x2, x2, x0
133 sub x2, x2, x1
255 sub x2, x3, x2
[all …]
/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/aarch64/
A Dplat_helpers.S24 adr x2, ptr_atf_crash_flag
25 ldr x2, [x2]
27 cbz x2, exit_putc
34 ldr x2, [x2]
37 str w1, [x2]
39 ldr w2, [x2]
51 add x1, x2, x1, LSR #6
54 ldr x2, [x2]
60 add x2, x2, x1, LSL # 3
63 ldr x1, [x2]
[all …]
/tf-a-ffa_el3_spmc/lib/romlib/
A Dinit.s21 adrp x2, __DATA_RAM_END__
22 add x2, x2, :lo12:__DATA_RAM_END__
23 sub x2, x2, x0
29 adrp x2, __BSS_END__
30 add x2, x2, :lo12:__BSS_END__
31 sub x2, x2, x0
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/
A Dplat_trampoline.S25 mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND
26 lsl x2, x2, #16
27 add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
28 cmp x1, x2
34 mov x2, #TEGRA194_STATE_SYSTEM_RESUME
35 add x1, x1, x2
43 ldr x2, [x2, #8]
47 cmp x2, #16
51 sub x2, x2, #16
55 cbz x2, boot_cpu
[all …]
/tf-a-ffa_el3_spmc/lib/extensions/amu/aarch64/
A Damu_helpers.S61 adr x2, 1f
76 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
78 br x2
136 adr x2, 1f
151 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
153 br x2
180 adr x2, 1f
199 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
201 br x2
289 br x2
[all …]
/tf-a-ffa_el3_spmc/plat/st/stm32mp1/services/
A Dbsec_svc.c16 uint32_t bsec_main(uint32_t x1, uint32_t x2, uint32_t x3, in bsec_main() argument
24 result = bsec_read_otp(ret_otp_value, x2); in bsec_main()
28 result = bsec_program_otp(x3, x2); in bsec_main()
32 result = bsec_write_otp(x3, x2); in bsec_main()
36 result = bsec_read_otp(&tmp_data, x2); in bsec_main()
41 result = bsec_shadow_register(x2); in bsec_main()
46 result = bsec_read_otp(ret_otp_value, x2); in bsec_main()
51 result = bsec_write_otp(tmp_data, x2); in bsec_main()
/tf-a-ffa_el3_spmc/plat/imx/common/
A Dimx_sip_svc.c21 u_register_t x2, in imx_sip_handler() argument
30 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
34 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
39 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
41 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
44 SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
47 return imx_otp_handler(smc_fid, handle, x1, x2); in imx_sip_handler()
49 SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
53 SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle)); in imx_sip_handler()
57 SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
A Dimx_sip_handler.c41 u_register_t x2, in imx_srtc_handler() argument
49 ret = imx_srtc_set_time(x2, x3, x4); in imx_srtc_handler()
72 u_register_t x2, in imx_cpufreq_handler() argument
77 imx_cpufreq_set_target(x2, x3); in imx_cpufreq_handler()
95 u_register_t x2, in imx_wakeup_src_handler() argument
115 u_register_t x2) in imx_otp_handler() argument
140 u_register_t x2, in imx_misc_set_temp_handler() argument
152 u_register_t x2, in imx_src_handler() argument
160 if (x2 != 0U) { in imx_src_handler()
206 u_register_t x2, in imx_buildinfo_handler() argument
[all …]
/tf-a-ffa_el3_spmc/plat/imx/common/include/
A Dimx_sip_svc.h38 u_register_t x2, u_register_t x3,
42 u_register_t x2, u_register_t x3);
47 u_register_t x2, u_register_t x3, void *handle);
52 u_register_t x2, u_register_t x3);
54 u_register_t x2, u_register_t x3, u_register_t x4);
56 u_register_t x2, u_register_t x3);
58 u_register_t x1, u_register_t x2);
60 u_register_t x2, u_register_t x3,
64 u_register_t x2, u_register_t x3,
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A Dplat_sip_calls.c40 uint64_t x2, in plat_sip_handler() argument
56 if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) in plat_sip_handler()
59 switch (x2) { in plat_sip_handler()
74 ERROR("%s: error offset=0x%llx\n", __func__, x2); in plat_sip_handler()
83 val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2)); in plat_sip_handler()
86 mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3); in plat_sip_handler()
/tf-a-ffa_el3_spmc/plat/mediatek/common/
A Dmtk_sip_svc.c27 u_register_t x2, in mediatek_plat_sip_handler() argument
42 u_register_t x2, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
68 (uint32_t)x2); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
93 u_register_t x2, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/aarch64/
A Dhikey_helpers.S48 mov_imm x2, PL011_BAUDRATE
89 ldr x2, =0xf7020000
91 str w1, [x2, #4]
93 str w1, [x2, #8]
95 str w1, [x2, #16]
97 str w1, [x2, #32]
99 mrs x2, currentel
100 and x2, x2, #0xc0
102 cmp x2, #0x04
/tf-a-ffa_el3_spmc/plat/marvell/armada/common/
A Dmrvl_sip_svc.c75 u_register_t x2, in mrvl_sip_smc_handler() argument
86 __func__, smc_fid, x1, x2, x3); in mrvl_sip_smc_handler()
99 if (x2 >= MAX_LANE_NR) { in mrvl_sip_smc_handler()
101 __func__, smc_fid, x2); in mrvl_sip_smc_handler()
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); in mrvl_sip_smc_handler()
115 ret = mvebu_cp110_comphy_power_off(x1, x2, x3); in mrvl_sip_smc_handler()
119 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2); in mrvl_sip_smc_handler()
123 ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2); in mrvl_sip_smc_handler()
150 ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3); in mrvl_sip_smc_handler()
154 ret = mvebu_dfx_misc_handle(x1, &read, x2, x3); in mrvl_sip_smc_handler()
[all …]
/tf-a-ffa_el3_spmc/lib/pmf/
A Dpmf_smc.c19 u_register_t x2, in pmf_smc_handler() argument
32 x2 = (uint32_t)x2; in pmf_smc_handler()
42 rc = pmf_get_timestamp_smc((unsigned int)x1, x2, in pmf_smc_handler()
55 rc = pmf_get_timestamp_smc((unsigned int)x1, x2, in pmf_smc_handler()
/tf-a-ffa_el3_spmc/lib/cpus/aarch64/
A Dcpu_helpers.S41 cbz x2, 1f
44 br x2
67 cmp x0, x2
68 csel x2, x2, x0, hi
130 cbz x2, 1f
131 blr x2
158 mrs x2, midr_el1
208 cbz x2, error_exit
209 mov x2, #0
248 csel x0, x2, x3, ls
[all …]
A Ddenver.S167 cmp x1, x2
187 cmp x1, x2
195 lsl x2, x1, #16
201 lsr x2, x2, #32
203 and x2, x2, x1
204 cbnz x2, 1b
220 mov x2, #0x10000
221 and x1, x1, x2
258 mrs x2, vbar_el3
259 csel x0, x1, x2, ne
[all …]
A Dcpuamu_helpers.S45 adr x2, 1f
46 add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
48 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
50 br x2
/tf-a-ffa_el3_spmc/plat/marvell/armada/a3k/common/
A Da3700_sip_svc.c31 u_register_t x2, in mrvl_sip_smc_handler() argument
41 __func__, smc_fid, x1, x2); in mrvl_sip_smc_handler()
45 __func__, smc_fid, x2); in mrvl_sip_smc_handler()
54 ret = mvebu_3700_comphy_power_on(x1, x2); in mrvl_sip_smc_handler()
58 ret = mvebu_3700_comphy_power_off(x1, x2); in mrvl_sip_smc_handler()
62 ret = mvebu_3700_comphy_is_pll_locked(x1, x2); in mrvl_sip_smc_handler()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/aarch64/
A Dhikey960_helpers.S52 mov_imm x2, PL011_BAUDRATE
93 ldr x2, =0xf7020000
95 str w1, [x2, #4]
97 str w1, [x2, #8]
99 str w1, [x2, #16]
101 str w1, [x2, #32]
103 mrs x2, currentel
104 and x2, x2, #0x0c
106 cmp x2, #0x04
/tf-a-ffa_el3_spmc/services/std_svc/
A Dstd_svc_setup.c80 u_register_t x2, in std_svc_smc_handler() argument
91 x2 &= UINT32_MAX; in std_svc_smc_handler()
115 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
133 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
149 … return spmc_smc_handler(smc_fid, is_caller_secure(flags), x1, x2, x3, x4, cookie, handle, flags); in std_svc_smc_handler()
152 return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
159 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
166 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
173 return pci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
/tf-a-ffa_el3_spmc/include/lib/pmf/aarch64/
A Dpmf_asm_macros.S21 adr x2, __PMF_PERCPU_TIMESTAMP_END__
23 sub x1, x2, x1
24 mov x2, #(\_tid * PMF_TS_SIZE)
25 madd x0, x0, x1, x2
/tf-a-ffa_el3_spmc/drivers/arm/css/sds/aarch64/
A Dsds_helpers.S54 ubfx x2, x2, #SDS_HEADER_STRUCT_SIZE_SHIFT, #SDS_HEADER_STRUCT_SIZE_WIDTH
56 add x2, x2, #SDS_HEADER_SIZE
57 add x0, x0, x2
/tf-a-ffa_el3_spmc/plat/arm/board/morello/aarch64/
A Dmorello_helper.S44 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
49 madd x2, x3, x4, x2
51 madd x1, x2, x4, x1
/tf-a-ffa_el3_spmc/lib/aarch64/
A Dmisc_helpers.S58 add x2, x0, x1
396 cmp x2, #16
400 sub x2, x2, #16
404 cbz x2, m_end
407 subs x2, x2, #1
518 adrp x2, __GOT_END__
519 add x2, x2, :lo12:__GOT_END__
540 cmp x1, x2
546 adrp x2, __RELA_END__
547 add x2, x2, :lo12:__RELA_END__
[all …]

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