Searched refs:A75 (Results 1 – 13 of 13) sorted by relevance
| /trusted-firmware-a/plat/arm/css/sgm/aarch64/ |
| A D | css_sgm_helpers.S | 62 jump_if_cpu_midr CORTEX_A75_MIDR, A75
70 A75: label
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| /trusted-firmware-a/plat/arm/css/sgi/aarch64/ |
| A D | sgi_helper.S | 69 jump_if_cpu_midr CORTEX_A75_MIDR, A75
79 A75: label
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| /trusted-firmware-a/docs/security_advisories/ |
| A D | security-advisory-tfv-6.rst | 51 For Cortex-A73 and Cortex-A75 CPUs, the PRs in this advisory invalidate the
55 is not effective at invalidating the branch predictor on Cortex-A73/Cortex-A75.
137 The only Arm CPU vulnerable to this variant is Cortex-A75.
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| A D | security-advisory-tfv-7.rst | 69 - Cortex-A75, by setting bit 35 (reserved in TRM) of ``CPUACTLR_EL1``
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/security_advisories/ |
| A D | security-advisory-tfv-6.rst.txt | 51 For Cortex-A73 and Cortex-A75 CPUs, the PRs in this advisory invalidate the
55 is not effective at invalidating the branch predictor on Cortex-A73/Cortex-A75.
137 The only Arm CPU vulnerable to this variant is Cortex-A75.
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| A D | security-advisory-tfv-7.rst.txt | 69 - Cortex-A75, by setting bit 35 (reserved in TRM) of ``CPUACTLR_EL1``
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| /trusted-firmware-a/docs/design/ |
| A D | cpu-specific-build-macros.rst | 210 For Cortex-A75, the following errata build flags are defined :
212 - ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
215 - ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | cpu-specific-build-macros.rst.txt | 210 For Cortex-A75, the following errata build flags are defined :
212 - ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
215 - ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/arm/fvp/ |
| A D | index.rst.txt | 351 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
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| /trusted-firmware-a/docs/plat/arm/fvp/ |
| A D | index.rst | 351 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/ |
| A D | change-log.md.txt | 3386 In addition to the v8.4 architectural extension, AMU support on Cortex-A75 was
3511 - Applied workarounds CVE-2017-5715 on Arm Cortex-A57, -A72, -A73 and -A75, and
3567 - Added support for Cortex-A75 and Cortex-A55 processors.
3569 Both Cortex-A75 and Cortex-A55 processors use the Arm DynamIQ Shared Unit
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| /trusted-firmware-a/docs/ |
| A D | change-log.md | 3386 In addition to the v8.4 architectural extension, AMU support on Cortex-A75 was
3511 - Applied workarounds CVE-2017-5715 on Arm Cortex-A57, -A72, -A73 and -A75, and
3567 - Added support for Cortex-A75 and Cortex-A55 processors.
3569 Both Cortex-A75 and Cortex-A55 processors use the Arm DynamIQ Shared Unit
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| /trusted-firmware-a/docs/build/latex/ |
| A D | trustedfirmware-a.tex | 26597 For Cortex\sphinxhyphen{}A75, the following errata build flags are defined :
26601 …inxupquote{ERRATA\_A75\_764081}}: This applies errata 764081 workaround to Cortex\sphinxhyphen{}A75
26605 …ATA\_A75\_790748}}: This applies errata 790748 workaround to Cortex\sphinxhyphen{}A75}] \leavevmode
34222 For use with models as the Cortex\sphinxhyphen{}A55\sphinxhyphen{}A75 Base FVPs with shifted affini…
45304 For Cortex\sphinxhyphen{}A73 and Cortex\sphinxhyphen{}A75 CPUs, the PRs in this advisory invalidate…
45308 …ffective at invalidating the branch predictor on Cortex\sphinxhyphen{}A73/Cortex\sphinxhyphen{}A75.
45444 The only Arm CPU vulnerable to this variant is Cortex\sphinxhyphen{}A75.
45575 Cortex\sphinxhyphen{}A75, by setting bit 35 (reserved in TRM) of \sphinxcode{\sphinxupquote{CPUACTL…
62128 In addition to the v8.4 architectural extension, AMU support on Cortex\sphinxhyphen{}A75 was
62493 Added support for Cortex\sphinxhyphen{}A75 and Cortex\sphinxhyphen{}A55 processors.
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