Home
last modified time | relevance | path

Searched refs:ARM_BL_RAM_BASE (Results 1 – 9 of 9) sorted by relevance

/trusted-firmware-a/plat/arm/board/a5ds/include/
A Dplatform_def.h33 #define ARM_BL_RAM_BASE (A5DS_SHARED_RAM_BASE + \ macro
157 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
159 - ARM_BL_RAM_BASE), \
202 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
203 #define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
209 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
221 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \
224 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
241 #define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
244 #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
/trusted-firmware-a/plat/arm/board/fvp_ve/include/
A Dplatform_def.h48 #define ARM_BL_RAM_BASE (FVP_VE_SHARED_RAM_BASE + \ macro
126 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
128 - ARM_BL_RAM_BASE), \
184 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
185 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
192 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
204 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \
207 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
227 #define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
230 #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
/trusted-firmware-a/plat/arm/board/corstone700/common/include/
A Dplatform_def.h65 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ macro
77 #define BL32_BASE (ARM_BL_RAM_BASE + PAGE_SIZE)
78 #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
92 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
93 #define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
106 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
220 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
222 - ARM_BL_RAM_BASE), \
/trusted-firmware-a/include/plat/arm/common/
A Darm_def.h71 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ macro
369 - ARM_BL_RAM_BASE), \
463 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
508 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \
512 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
528 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
569 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
579 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
608 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
611 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
[all …]
/trusted-firmware-a/plat/arm/board/diphda/common/include/
A Dplatform_def.h158 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ macro
169 #define BL2_LIMIT (ARM_BL_RAM_BASE + \
181 #define BL32_BASE ARM_BL_RAM_BASE
234 #define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE
/trusted-firmware-a/plat/arm/common/
A Darm_bl2_el3_setup.c39 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE; in arm_bl2_el3_early_platform_setup()
A Darm_dyn_cfg.c181 if (image_base < ARM_BL_RAM_BASE) { in arm_bl2_dyn_cfg_init()
A Darm_bl1_setup.c83 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; in arm_bl1_early_platform_setup()
/trusted-firmware-a/plat/arm/board/fvp_r/
A Dfvp_r_bl1_setup.c71 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; in arm_bl1_early_platform_setup()

Completed in 17 milliseconds