Home
last modified time | relevance | path

Searched refs:ARM_SYS_CNTCTL_BASE (Results 1 – 13 of 13) sorted by relevance

/trusted-firmware-a/plat/arm/common/
A Darm_common.c174 #ifdef ARM_SYS_CNTCTL_BASE
181 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
A Darm_bl31_setup.c282 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in arm_bl31_platform_setup()
/trusted-firmware-a/plat/arm/common/sp_min/
A Darm_sp_min_setup.c201 #ifdef ARM_SYS_CNTCTL_BASE in sp_min_platform_setup()
202 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in sp_min_platform_setup()
/trusted-firmware-a/plat/arm/board/fvp/
A Dfvp_bl31_setup.c97 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
A Dfvp_common.c472 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in fvp_timer_init()
/trusted-firmware-a/plat/arm/board/fvp_r/
A Dfvp_r_common.c267 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in fvp_timer_init()
/trusted-firmware-a/include/plat/arm/common/
A Darm_def.h391 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE macro
393 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) macro
/trusted-firmware-a/plat/arm/board/corstone700/common/include/
A Dplatform_def.h127 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) macro
/trusted-firmware-a/plat/arm/board/diphda/common/include/
A Dplatform_def.h258 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) macro
/trusted-firmware-a/plat/renesas/common/aarch64/
A Dplatform_common.c207 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
/trusted-firmware-a/plat/renesas/common/include/
A Drcar_def.h206 #define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE macro
/trusted-firmware-a/plat/renesas/rzg/
A Dbl2_plat_setup.c1016 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); in bl2_init_generic_timer()
/trusted-firmware-a/plat/renesas/rcar/
A Dbl2_plat_setup.c1195 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); in bl2_init_generic_timer()

Completed in 16 milliseconds