| /trusted-firmware-a/bl1/ |
| A D | bl1.ld.S | 24 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
94 . = BL1_RW_BASE; define
95 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
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| A D | bl1_main.c | 47 assert(BL1_RW_BASE > bl1_mem_layout->total_base); in bl1_calc_bl2_mem_layout()
49 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; in bl1_calc_bl2_mem_layout()
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| /trusted-firmware-a/plat/hisilicon/poplar/include/ |
| A D | poplar_layout.h | 121 #define BL1_RW_BASE (LLOADER_TEXT_BASE + BL1_RW_OFFSET) macro
122 #define BL1_RW_LIMIT (BL1_RW_BASE + BL1_RW_SIZE)
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| /trusted-firmware-a/plat/hisilicon/hikey960/aarch64/ |
| A D | hikey960_common.c | 29 #define MAP_BL1_RW MAP_REGION_FLAT(BL1_RW_BASE, \
30 BL1_RW_LIMIT - BL1_RW_BASE, \
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| /trusted-firmware-a/include/plat/marvell/armada/a3k/common/ |
| A D | marvell_def.h | 148 #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ macro
173 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
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| /trusted-firmware-a/include/plat/arm/common/ |
| A D | arm_def.h | 315 BL1_RW_BASE, \
316 BL1_RW_LIMIT - BL1_RW_BASE, \
508 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
518 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
534 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
535 #define BL2_LIMIT BL1_RW_BASE
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| /trusted-firmware-a/include/plat/marvell/armada/a8k/common/ |
| A D | marvell_def.h | 179 #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ macro
208 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
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| /trusted-firmware-a/plat/arm/board/a5ds/include/ |
| A D | platform_def.h | 221 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
233 #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE)
234 #define BL2_LIMIT BL1_RW_BASE
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| /trusted-firmware-a/plat/arm/board/fvp_ve/include/ |
| A D | platform_def.h | 204 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ macro
218 #define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE)
219 #define BL2_LIMIT BL1_RW_BASE
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| /trusted-firmware-a/plat/layerscape/board/ls1043/include/ |
| A D | platform_def.h | 125 #define BL1_RW_BASE BL2_LIMIT macro
127 #define BL1_RW_BASE BL31_LIMIT macro
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| /trusted-firmware-a/plat/qemu/qemu_sbsa/include/ |
| A D | platform_def.h | 118 #define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE) macro
139 #define BL31_LIMIT (BL1_RW_BASE)
140 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
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| /trusted-firmware-a/plat/brcm/board/stingray/include/ |
| A D | platform_def.h | 101 #define BL1_RW_BASE (BRCM_BL_RAM_BASE) macro
102 #define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000)
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| /trusted-firmware-a/plat/arm/board/fvp_r/ |
| A D | fvp_r_bl1_main.c | 108 assert(bl1_mem_layout->total_base < BL1_RW_BASE); in bl1_calc_bl2_mem_layout()
110 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; in bl1_calc_bl2_mem_layout()
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| /trusted-firmware-a/plat/rpi/rpi3/include/ |
| A D | platform_def.h | 171 #define BL1_RW_BASE (BL1_RW_LIMIT - PLAT_MAX_BL1_RW_SIZE) macro
195 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
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| /trusted-firmware-a/plat/qemu/qemu/include/ |
| A D | platform_def.h | 131 #define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) macro
151 #define BL31_PROGBITS_LIMIT BL1_RW_BASE
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| /trusted-firmware-a/plat/hisilicon/hikey/include/ |
| A D | hikey_layout.h | 40 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_8000 */ macro
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| /trusted-firmware-a/plat/hisilicon/hikey960/include/ |
| A D | platform_def.h | 54 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC2_0000 */ macro
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| /trusted-firmware-a/plat/hisilicon/poplar/ |
| A D | bl1_plat_setup.c | 76 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
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| /trusted-firmware-a/plat/hisilicon/hikey/ |
| A D | hikey_bl1_setup.c | 55 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
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| /trusted-firmware-a/plat/intel/soc/common/include/ |
| A D | platform_def.h | 122 #define BL1_RW_BASE (0xffe10000) macro
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| /trusted-firmware-a/build/qemu/release/bl1/ |
| A D | bl1.ld | 38 "BL1_RW_BASE address is not aligned on a page boundary.")
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| A D | bl1.map | 1161 …0000000000000001 ASSERT ((0xe04e000 == ALIGN (0x1000)), BL1_RW_BASE address is not …
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| /trusted-firmware-a/plat/hisilicon/hikey960/ |
| A D | hikey960_bl1_setup.c | 87 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
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| /trusted-firmware-a/docs/design/ |
| A D | firmware-design.rst | 144 to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
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| /trusted-firmware-a/docs/build/TF-A_2.5/_sources/design/ |
| A D | firmware-design.rst.txt | 144 to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
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