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Searched refs:BL2_BASE (Results 1 – 25 of 47) sorted by relevance

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/trusted-firmware-a/plat/brcm/board/stingray/include/
A Dplatform_def.h112 #define BL2_BASE QSPI_BASE_ADDR macro
113 #define BL2_LIMIT (BL2_BASE + 0x40000)
118 #define BL2_BASE NAND_BASE_ADDR macro
119 #define BL2_LIMIT (BL2_BASE + 0x40000)
124 #define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE) macro
/trusted-firmware-a/tools/nxp/create_pbl/
A Dpbl_ch2.mk25 …BL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
46 …L} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
A Dpbl_ch3.mk33 …BL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
62 …L} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
/trusted-firmware-a/include/plat/arm/css/common/
A Dcss_def.h184 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
185 #define SCP_BL2_LIMIT BL2_BASE
187 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
188 #define SCP_BL2U_LIMIT BL2_BASE
/trusted-firmware-a/include/plat/common/
A Dcommon_def.h40 .image_info.image_base = BL2_BASE, \
41 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\
44 .ep_info.pc = BL2_BASE, \
/trusted-firmware-a/plat/layerscape/board/ls1043/include/
A Dplatform_def.h109 #define BL2_BASE (BL31_BASE + BL31_TEXT_RODATA_SIZE) macro
110 #define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
116 #define BL2_BASE LS_BL2_DDR_BASE macro
117 #define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
/trusted-firmware-a/plat/renesas/common/include/
A Dplatform_def.h115 #define BL2_BASE U(0xE6304000) macro
118 #define BL2_BASE U(0xE6344000) macro
121 #define BL2_BASE U(0xE6304000) macro
124 #define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
/trusted-firmware-a/bl2/
A Dbl2.ld.S15 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
21 . = BL2_BASE; define
A Dbl2_el3.ld.S19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
34 . = BL2_BASE; define
/trusted-firmware-a/include/drivers/arm/css/
A Dcss_scp.h45 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
46 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
/trusted-firmware-a/plat/hisilicon/poplar/include/
A Dpoplar_layout.h125 #define BL2_BASE (LLOADER_TEXT_BASE + BL2_OFFSET) macro
126 #define BL2_LIMIT (BL2_BASE + BL2_SIZE)
/trusted-firmware-a/plat/socionext/uniphier/include/
A Dplatform_def.h53 #define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET) macro
54 #define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE)
/trusted-firmware-a/plat/nxp/common/plat_make_helper/
A Dsoc_common_def.mk52 ifneq (${BL2_BASE},)
53 $(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
/trusted-firmware-a/plat/hisilicon/hikey960/include/
A Dplatform_def.h61 #define BL2_BASE (0x1AC00000) macro
62 #define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
/trusted-firmware-a/bl1/tbbr/
A Dtbbr_img_desc.c17 .image_info.image_base = BL2_BASE,
18 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,
/trusted-firmware-a/include/plat/arm/common/
A Darm_def.h526 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ macro
534 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) macro
553 #define BL31_NOBITS_BASE BL2_BASE
571 #define BL31_PROGBITS_LIMIT BL2_BASE
577 #define BL31_LIMIT BL2_BASE
610 # define BL32_PROGBITS_LIMIT BL2_BASE
680 #define BL2U_BASE BL2_BASE
/trusted-firmware-a/plat/hisilicon/poplar/
A Dbl1_plat_setup.c56 bl2_tzram_layout.total_base = BL2_BASE; in bl1_plat_handle_post_image_load()
57 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; in bl1_plat_handle_post_image_load()
/trusted-firmware-a/plat/nxp/soc-ls1028a/
A Dsoc.def64 BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
66 # BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD)
68 # overalp with BL2_BASE
/trusted-firmware-a/drivers/arm/css/scp/
A Dcss_bom_bootloader.c56 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
57 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
/trusted-firmware-a/plat/intel/soc/agilex/
A Dbl2_plat_setup.c92 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
/trusted-firmware-a/plat/intel/soc/stratix10/
A Dbl2_plat_setup.c88 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
/trusted-firmware-a/bl2/aarch64/
A Dbl2_el3_entrypoint.S19 #define FIXUP_SIZE ((BL2_LIMIT) - (BL2_BASE))
/trusted-firmware-a/plat/arm/board/a5ds/include/
A Dplatform_def.h233 #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE) macro
243 #define BL32_PROGBITS_LIMIT BL2_BASE
/trusted-firmware-a/plat/arm/board/fvp_ve/include/
A Dplatform_def.h218 #define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE) macro
229 #define BL32_PROGBITS_LIMIT BL2_BASE
/trusted-firmware-a/plat/nxp/common/setup/
A Dls_bl2_el3_setup.c189 BL2_BASE, in ls_bl2_el3_plat_arch_setup()
190 (unsigned long)(&__BL2_END__) - BL2_BASE, in ls_bl2_el3_plat_arch_setup()

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