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Searched refs:CACHE_WRITEBACK_GRANULE (Results 1 – 25 of 98) sorted by relevance

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/trusted-firmware-a/include/common/
A Dbl_common.ld.h157 . = ALIGN(CACHE_WRITEBACK_GRANULE); \
161 . = ALIGN(CACHE_WRITEBACK_GRANULE); \
179 . = ALIGN(CACHE_WRITEBACK_GRANULE); \
182 . = ALIGN(CACHE_WRITEBACK_GRANULE); \
/trusted-firmware-a/include/lib/el3_runtime/
A Dcpu_data.h64 CACHE_WRITEBACK_GRANULE - 1) / \
65 CACHE_WRITEBACK_GRANULE) * \
66 CACHE_WRITEBACK_GRANULE)
140 } __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t;
/trusted-firmware-a/plat/layerscape/board/ls1043/include/
A Dls_def.h100 #define CACHE_WRITEBACK_GRANULE (1 << LS_CACHE_WRITEBACK_SHIFT) macro
105 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
/trusted-firmware-a/plat/nvidia/tegra/scat/
A Dbl31.scat181 __BAKERY_LOCKS__ AlignExpr(ImageLimit(__BSS__), CACHE_WRITEBACK_GRANULE) FIXED
186 …__BAKERY_LOCKS_EPILOGUE__ AlignExpr(ImageLimit(__BAKERY_LOCKS__), CACHE_WRITEBACK_GRANULE) FIXED E…
210 __PMF_TIMESTAMP__ AlignExpr(+0, CACHE_WRITEBACK_GRANULE) FIXED EMPTY CACHE_WRITEBACK_GRANULE
215 …__PMF_TIMESTAMP_EPILOGUE__ AlignExpr(ImageLimit(__PMF_TIMESTAMP__), CACHE_WRITEBACK_GRANULE) FIXED…
219 * CACHE_WRITEBACK_GRANULE boundary
/trusted-firmware-a/plat/qti/sc7180/inc/
A Dplatform_def.h94 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) macro
99 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
/trusted-firmware-a/plat/qti/sc7280/inc/
A Dplatform_def.h94 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) macro
99 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
/trusted-firmware-a/plat/nxp/common/plat_make_helper/
A Dsoc_common_def.mk10 $(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
11 $(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
/trusted-firmware-a/drivers/nxp/crypto/caam/src/auth/
A Drsa.c41 struct rsa_context ctx __aligned(CACHE_WRITEBACK_GRANULE); in rsa_public_verif_sec()
42 struct job_descriptor jobdesc __aligned(CACHE_WRITEBACK_GRANULE); in rsa_public_verif_sec()
155 uint8_t encoded_hash[RSA_4K_KEY_SZ_BYTES] __aligned(CACHE_WRITEBACK_GRANULE); in rsa_verify_signature()
/trusted-firmware-a/plat/arm/board/fvp_r/
A Dfvp_r_bl1_main.c213 assert(SIZE_FROM_LOG2_WORDS(val) == CACHE_WRITEBACK_GRANULE); in bl1_main()
215 assert(MAX_CACHE_LINE_SIZE >= CACHE_WRITEBACK_GRANULE); in bl1_main()
/trusted-firmware-a/bl32/tsp/
A Dtsp_private.h48 } __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t;
52 } __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t;
/trusted-firmware-a/plat/common/aarch32/
A Dplatform_up_stack.S47 PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE
/trusted-firmware-a/plat/common/aarch64/
A Dplatform_up_stack.S50 PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE
A Dplatform_mp_stack.S61 CACHE_WRITEBACK_GRANULE
/trusted-firmware-a/bl1/
A Dbl1_main.c116 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); in bl1_main()
118 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); in bl1_main()
/trusted-firmware-a/drivers/nxp/crypto/caam/src/
A Drng.c100 struct job_descriptor desc __aligned(CACHE_WRITEBACK_GRANULE); in instantiate_rng()
133 struct job_descriptor desc __aligned(CACHE_WRITEBACK_GRANULE); in hw_rng_generate()
A Dsec_jr_driver.c32 uint8_t ip_ring[SEC_DMA_MEM_INPUT_RING_SIZE] __aligned(CACHE_WRITEBACK_GRANULE);
33 uint8_t op_ring[SEC_DMA_MEM_OUTPUT_RING_SIZE] __aligned(CACHE_WRITEBACK_GRANULE);
/trusted-firmware-a/services/std_svc/rmmd/trp/
A Dtrp_private.h29 } __aligned(CACHE_WRITEBACK_GRANULE) trp_args_t;
/trusted-firmware-a/plat/hisilicon/hikey/include/
A Dplatform_def.h83 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) macro
/trusted-firmware-a/plat/amlogic/g12a/include/
A Dplatform_def.h54 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) macro
/trusted-firmware-a/plat/amlogic/gxl/include/
A Dplatform_def.h54 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) macro
/trusted-firmware-a/plat/amlogic/gxbb/include/
A Dplatform_def.h57 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) macro
/trusted-firmware-a/plat/amlogic/axg/include/
A Dplatform_def.h57 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) macro
/trusted-firmware-a/plat/imx/imx8qx/include/
A Dplatform_def.h16 #define CACHE_WRITEBACK_GRANULE 64 macro
/trusted-firmware-a/plat/rockchip/rk3288/include/
A Dplatform_def.h82 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) macro
/trusted-firmware-a/plat/imx/imx8qm/include/
A Dplatform_def.h16 #define CACHE_WRITEBACK_GRANULE 64 macro

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