1 /*
2  * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /*
8  * ZynqMP system level PM-API functions for clock control.
9  */
10 
11 #ifndef PM_API_CLOCK_H
12 #define PM_API_CLOCK_H
13 
14 #include <lib/utils_def.h>
15 
16 #include "pm_common.h"
17 
18 #define CLK_NAME_LEN		U(15)
19 #define MAX_PARENTS		U(100)
20 #define CLK_NA_PARENT		-1
21 #define CLK_DUMMY_PARENT	-2
22 
23 /* Flags for parent id */
24 #define PARENT_CLK_SELF		U(0)
25 #define PARENT_CLK_NODE1	U(1)
26 #define PARENT_CLK_NODE2	U(2)
27 #define PARENT_CLK_NODE3	U(3)
28 #define PARENT_CLK_NODE4	U(4)
29 #define PARENT_CLK_EXTERNAL	U(5)
30 #define PARENT_CLK_MIO0_MIO77	U(6)
31 
32 #define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
33 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
34 #define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
35 #define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
36 /* unused */
37 #define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
38 #define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
39 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
40 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
41 #define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
42 #define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
43 #define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
44 /* parents need enable during gate/ungate, set rate and re-parent */
45 #define CLK_OPS_PARENT_ENABLE	BIT(12)
46 
47 #define CLK_DIVIDER_ONE_BASED		BIT(0)
48 #define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
49 #define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
50 #define CLK_DIVIDER_HIWORD_MASK		BIT(3)
51 #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
52 #define CLK_DIVIDER_READ_ONLY		BIT(5)
53 #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
54 #define CLK_FRAC		BIT(8)
55 
56 #define END_OF_CLK     "END_OF_CLK"
57 
58 //CLock Ids
59 enum clock_id {
60 	CLK_IOPLL,
61 	CLK_RPLL,
62 	CLK_APLL,
63 	CLK_DPLL,
64 	CLK_VPLL,
65 	CLK_IOPLL_TO_FPD,
66 	CLK_RPLL_TO_FPD,
67 	CLK_APLL_TO_LPD,
68 	CLK_DPLL_TO_LPD,
69 	CLK_VPLL_TO_LPD,
70 	CLK_ACPU,
71 	CLK_ACPU_HALF,
72 	CLK_DBG_FPD,
73 	CLK_DBG_LPD,
74 	CLK_DBG_TRACE,
75 	CLK_DBG_TSTMP,
76 	CLK_DP_VIDEO_REF,
77 	CLK_DP_AUDIO_REF,
78 	CLK_DP_STC_REF,
79 	CLK_GDMA_REF,
80 	CLK_DPDMA_REF,
81 	CLK_DDR_REF,
82 	CLK_SATA_REF,
83 	CLK_PCIE_REF,
84 	CLK_GPU_REF,
85 	CLK_GPU_PP0_REF,
86 	CLK_GPU_PP1_REF,
87 	CLK_TOPSW_MAIN,
88 	CLK_TOPSW_LSBUS,
89 	CLK_GTGREF0_REF,
90 	CLK_LPD_SWITCH,
91 	CLK_LPD_LSBUS,
92 	CLK_USB0_BUS_REF,
93 	CLK_USB1_BUS_REF,
94 	CLK_USB3_DUAL_REF,
95 	CLK_USB0,
96 	CLK_USB1,
97 	CLK_CPU_R5,
98 	CLK_CPU_R5_CORE,
99 	CLK_CSU_SPB,
100 	CLK_CSU_PLL,
101 	CLK_PCAP,
102 	CLK_IOU_SWITCH,
103 	CLK_GEM_TSU_REF,
104 	CLK_GEM_TSU,
105 	CLK_GEM0_TX,
106 	CLK_GEM1_TX,
107 	CLK_GEM2_TX,
108 	CLK_GEM3_TX,
109 	CLK_GEM0_RX,
110 	CLK_GEM1_RX,
111 	CLK_GEM2_RX,
112 	CLK_GEM3_RX,
113 	CLK_QSPI_REF,
114 	CLK_SDIO0_REF,
115 	CLK_SDIO1_REF,
116 	CLK_UART0_REF,
117 	CLK_UART1_REF,
118 	CLK_SPI0_REF,
119 	CLK_SPI1_REF,
120 	CLK_NAND_REF,
121 	CLK_I2C0_REF,
122 	CLK_I2C1_REF,
123 	CLK_CAN0_REF,
124 	CLK_CAN1_REF,
125 	CLK_CAN0,
126 	CLK_CAN1,
127 	CLK_DLL_REF,
128 	CLK_ADMA_REF,
129 	CLK_TIMESTAMP_REF,
130 	CLK_AMS_REF,
131 	CLK_PL0_REF,
132 	CLK_PL1_REF,
133 	CLK_PL2_REF,
134 	CLK_PL3_REF,
135 	CLK_FPD_WDT,
136 	CLK_IOPLL_INT,
137 	CLK_IOPLL_PRE_SRC,
138 	CLK_IOPLL_HALF,
139 	CLK_IOPLL_INT_MUX,
140 	CLK_IOPLL_POST_SRC,
141 	CLK_RPLL_INT,
142 	CLK_RPLL_PRE_SRC,
143 	CLK_RPLL_HALF,
144 	CLK_RPLL_INT_MUX,
145 	CLK_RPLL_POST_SRC,
146 	CLK_APLL_INT,
147 	CLK_APLL_PRE_SRC,
148 	CLK_APLL_HALF,
149 	CLK_APLL_INT_MUX,
150 	CLK_APLL_POST_SRC,
151 	CLK_DPLL_INT,
152 	CLK_DPLL_PRE_SRC,
153 	CLK_DPLL_HALF,
154 	CLK_DPLL_INT_MUX,
155 	CLK_DPLL_POST_SRC,
156 	CLK_VPLL_INT,
157 	CLK_VPLL_PRE_SRC,
158 	CLK_VPLL_HALF,
159 	CLK_VPLL_INT_MUX,
160 	CLK_VPLL_POST_SRC,
161 	CLK_CAN0_MIO,
162 	CLK_CAN1_MIO,
163 	CLK_ACPU_FULL,
164 	CLK_GEM0_REF,
165 	CLK_GEM1_REF,
166 	CLK_GEM2_REF,
167 	CLK_GEM3_REF,
168 	CLK_GEM0_REF_UNGATED,
169 	CLK_GEM1_REF_UNGATED,
170 	CLK_GEM2_REF_UNGATED,
171 	CLK_GEM3_REF_UNGATED,
172 	CLK_LPD_WDT,
173 	END_OF_OUTPUT_CLKS,
174 };
175 
176 #define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS)
177 
178 //External clock ids
179 enum {
180 	EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
181 	EXT_CLK_VIDEO,
182 	EXT_CLK_PSS_ALT_REF,
183 	EXT_CLK_AUX_REF,
184 	EXT_CLK_GT_CRX_REF,
185 	EXT_CLK_SWDT0,
186 	EXT_CLK_SWDT1,
187 	EXT_CLK_GEM0_TX_EMIO,
188 	EXT_CLK_GEM1_TX_EMIO,
189 	EXT_CLK_GEM2_TX_EMIO,
190 	EXT_CLK_GEM3_TX_EMIO,
191 	EXT_CLK_GEM0_RX_EMIO,
192 	EXT_CLK_GEM1_RX_EMIO,
193 	EXT_CLK_GEM2_RX_EMIO,
194 	EXT_CLK_GEM3_RX_EMIO,
195 	EXT_CLK_MIO50_OR_MIO51,
196 	EXT_CLK_MIO0,
197 	EXT_CLK_MIO1,
198 	EXT_CLK_MIO2,
199 	EXT_CLK_MIO3,
200 	EXT_CLK_MIO4,
201 	EXT_CLK_MIO5,
202 	EXT_CLK_MIO6,
203 	EXT_CLK_MIO7,
204 	EXT_CLK_MIO8,
205 	EXT_CLK_MIO9,
206 	EXT_CLK_MIO10,
207 	EXT_CLK_MIO11,
208 	EXT_CLK_MIO12,
209 	EXT_CLK_MIO13,
210 	EXT_CLK_MIO14,
211 	EXT_CLK_MIO15,
212 	EXT_CLK_MIO16,
213 	EXT_CLK_MIO17,
214 	EXT_CLK_MIO18,
215 	EXT_CLK_MIO19,
216 	EXT_CLK_MIO20,
217 	EXT_CLK_MIO21,
218 	EXT_CLK_MIO22,
219 	EXT_CLK_MIO23,
220 	EXT_CLK_MIO24,
221 	EXT_CLK_MIO25,
222 	EXT_CLK_MIO26,
223 	EXT_CLK_MIO27,
224 	EXT_CLK_MIO28,
225 	EXT_CLK_MIO29,
226 	EXT_CLK_MIO30,
227 	EXT_CLK_MIO31,
228 	EXT_CLK_MIO32,
229 	EXT_CLK_MIO33,
230 	EXT_CLK_MIO34,
231 	EXT_CLK_MIO35,
232 	EXT_CLK_MIO36,
233 	EXT_CLK_MIO37,
234 	EXT_CLK_MIO38,
235 	EXT_CLK_MIO39,
236 	EXT_CLK_MIO40,
237 	EXT_CLK_MIO41,
238 	EXT_CLK_MIO42,
239 	EXT_CLK_MIO43,
240 	EXT_CLK_MIO44,
241 	EXT_CLK_MIO45,
242 	EXT_CLK_MIO46,
243 	EXT_CLK_MIO47,
244 	EXT_CLK_MIO48,
245 	EXT_CLK_MIO49,
246 	EXT_CLK_MIO50,
247 	EXT_CLK_MIO51,
248 	EXT_CLK_MIO52,
249 	EXT_CLK_MIO53,
250 	EXT_CLK_MIO54,
251 	EXT_CLK_MIO55,
252 	EXT_CLK_MIO56,
253 	EXT_CLK_MIO57,
254 	EXT_CLK_MIO58,
255 	EXT_CLK_MIO59,
256 	EXT_CLK_MIO60,
257 	EXT_CLK_MIO61,
258 	EXT_CLK_MIO62,
259 	EXT_CLK_MIO63,
260 	EXT_CLK_MIO64,
261 	EXT_CLK_MIO65,
262 	EXT_CLK_MIO66,
263 	EXT_CLK_MIO67,
264 	EXT_CLK_MIO68,
265 	EXT_CLK_MIO69,
266 	EXT_CLK_MIO70,
267 	EXT_CLK_MIO71,
268 	EXT_CLK_MIO72,
269 	EXT_CLK_MIO73,
270 	EXT_CLK_MIO74,
271 	EXT_CLK_MIO75,
272 	EXT_CLK_MIO76,
273 	EXT_CLK_MIO77,
274 	END_OF_CLKS,
275 };
276 
277 #define CLK_MAX (unsigned int)(END_OF_CLKS)
278 
279 //CLock types
280 #define CLK_TYPE_OUTPUT 0U
281 #define	CLK_TYPE_EXTERNAL  1U
282 
283 //Topology types
284 #define TYPE_INVALID 0U
285 #define	TYPE_MUX 1U
286 #define	TYPE_PLL 2U
287 #define	TYPE_FIXEDFACTOR 3U
288 #define	TYPE_DIV1 4U
289 #define	TYPE_DIV2 5U
290 #define	TYPE_GATE 6U
291 
292 struct pm_pll;
293 struct pm_pll *pm_clock_get_pll(enum clock_id clock_id);
294 struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id);
295 uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id);
296 
297 void pm_api_clock_get_name(unsigned int clock_id, char *name);
298 enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks);
299 enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
300 					     unsigned int index,
301 					     uint32_t *topology);
302 enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id,
303 						       uint32_t *mul,
304 						       uint32_t *div);
305 enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
306 					    unsigned int index,
307 					    uint32_t *parents);
308 enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
309 					       uint32_t *attr);
310 enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id,
311 						uint8_t div_type,
312 						uint32_t *max_div);
313 
314 enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id,
315 					    enum pm_node_id *node_id);
316 enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id);
317 
318 enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
319 enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
320 enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
321 					  unsigned int *state);
322 enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll,
323 					   enum clock_id clock_id,
324 					   unsigned int parent_index);
325 enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
326 					   enum clock_id clock_id,
327 					   unsigned int *parent_index);
328 enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
329 					 unsigned int mode);
330 enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id,
331 					 unsigned int *mode);
332 
333 #endif /* PM_API_CLOCK_H */
334