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Searched refs:CLK_SET_RATE_GATE (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a/plat/xilinx/zynqmp/pm_service/
A Dpm_api_clock.h32 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ macro
A Dpm_api_clock.c179 CLK_SET_RATE_GATE | \
417 CLK_SET_RATE_GATE |
434 CLK_SET_RATE_GATE,

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