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Searched refs:CNTFID_OFF (Results 1 – 11 of 11) sorted by relevance

/trusted-firmware-a/plat/arm/board/fvp/
A Dfvp_bl31_setup.c97 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
/trusted-firmware-a/plat/arm/common/
A Darm_common.c181 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
/trusted-firmware-a/plat/socionext/synquacer/
A Dsq_bl31_setup.c193 counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
/trusted-firmware-a/plat/renesas/common/aarch64/
A Dplatform_common.c207 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
/trusted-firmware-a/plat/nxp/soc-ls1028a/
A Dsoc.c81 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); in plat_get_syscnt_freq2()
/trusted-firmware-a/plat/nxp/soc-lx2160a/
A Dsoc.c104 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); in plat_get_syscnt_freq2()
/trusted-firmware-a/drivers/st/clk/
A Dstm32mp1_clk.c1680 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); in stm32mp1_stgen_config()
1694 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); in stm32mp1_stgen_config()
1710 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; in stm32mp1_stgen_increment()
/trusted-firmware-a/plat/renesas/rzg/
A Dbl2_plat_setup.c1016 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); in bl2_init_generic_timer()
/trusted-firmware-a/include/arch/aarch32/
A Darch.h88 #define CNTFID_OFF U(0x020) macro
/trusted-firmware-a/plat/renesas/rcar/
A Dbl2_plat_setup.c1195 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); in bl2_init_generic_timer()
/trusted-firmware-a/include/arch/aarch64/
A Darch.h130 #define CNTFID_OFF U(0x020) macro

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