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Searched refs:CPU_PLLDIV_CFG0 (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a/plat/mediatek/mt8192/drivers/dcm/
A Dmtk_dcm_utils.c238 ret &= ((mmio_read_32(CPU_PLLDIV_CFG0) & in dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on()
249 mmio_clrsetbits_32(CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm()
254 mmio_clrsetbits_32(CPU_PLLDIV_CFG0, in dcm_mp_cpusys_top_cpu_pll_div_0_dcm()
A Dmtk_dcm_utils.h20 #define CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) macro

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