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Searched refs:CPU_PLLDIV_CFG1 (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a/plat/mediatek/mt8192/drivers/dcm/
A Dmtk_dcm_utils.c268 ret &= ((mmio_read_32(CPU_PLLDIV_CFG1) & in dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on()
279 mmio_clrsetbits_32(CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm()
284 mmio_clrsetbits_32(CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm()
A Dmtk_dcm_utils.h21 #define CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) macro

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