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Searched refs:CTLR_ENABLE_G0_BIT (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-a/drivers/arm/gic/v2/
A Dgicv2_main.c45 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; in gicv2_cpuif_enable()
66 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); in gicv2_cpuif_disable()
89 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) { in gicv2_pcpu_distif_init()
91 ctlr | CTLR_ENABLE_G0_BIT); in gicv2_pcpu_distif_init()
110 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); in gicv2_distif_init()
121 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); in gicv2_distif_init()
/trusted-firmware-a/drivers/arm/gic/v3/
A Dgic600_multichip.c47 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in set_gicd_dchipr_rt_owner()
83 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in set_gicd_chipr_n()
218 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in gic600_multichip_init()
A Dgicv3_helpers.c230 ctlr_enable |= CTLR_ENABLE_G0_BIT; in gicv3_secure_spis_config_props()
342 ctlr_enable |= CTLR_ENABLE_G0_BIT; in gicv3_secure_ppi_sgi_config_props()
A Dgicv3_main.c196 CTLR_ENABLE_G0_BIT | in gicv3_distif_init()
829 CTLR_ENABLE_G0_BIT | in gicv3_distif_init_restore()
/trusted-firmware-a/include/drivers/arm/
A Dgic_common.h62 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT) macro

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