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Searched refs:DVFSRC_BASE (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-a/plat/mediatek/mt8195/drivers/spm/
A Dmt_spm_vcorefs.h72 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
73 #define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4)
74 #define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8)
75 #define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC)
76 #define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10)
77 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
78 #define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18)
79 #define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C)
80 #define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20)
81 #define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24)
[all …]
/trusted-firmware-a/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_vcorefs.h50 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
51 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
52 #define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
53 #define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
54 #define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0)
55 #define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
56 #define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
57 #define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
58 #define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
59 #define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
[all …]
/trusted-firmware-a/plat/mediatek/mt8195/include/
A Dplatform_def.h36 #define DVFSRC_BASE (IO_PHYS + 0x00012000) macro
/trusted-firmware-a/plat/mediatek/mt8192/include/
A Dplatform_def.h44 #define DVFSRC_BASE (IO_PHYS + 0x00012000) macro
/trusted-firmware-a/plat/mediatek/mt8183/include/
A Dplatform_def.h35 #define DVFSRC_BASE (IO_PHYS + 0x12000) macro

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