Searched refs:EL1_EL0_REGIME (Results 1 – 11 of 11) sorted by relevance
102 tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME; in init_xlat_tables()144 if (tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME) { in xlat_make_tables_readonly()156 assert(tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME); in xlat_make_tables_readonly()174 if (tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME) { in xlat_make_tables_readonly()215 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); in enable_mmu_el1()258 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); in enable_mmu_svc_mon()
71 assert(xlat_regime == EL1_EL0_REGIME); in xlat_desc_print()82 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME); in xlat_desc_print()226 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_tables_print()358 assert((ctx->xlat_regime == EL1_EL0_REGIME) || in xlat_get_mem_attributes_internal()414 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_get_mem_attributes_internal()
143 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_desc()1194 (ctx->xlat_regime == EL1_EL0_REGIME)); in init_xlat_tables_ctx()
77 if (ctx->xlat_regime == EL1_EL0_REGIME) { in is_mmu_enabled_ctx()98 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_regime_get_xn_desc()114 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_tlbi_va()193 if (xlat_regime == EL1_EL0_REGIME) { in setup_mmu_cfg()
150 if (ctx->xlat_regime == EL1_EL0_REGIME) { in is_mmu_enabled_ctx()178 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_regime_get_xn_desc()202 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_tlbi_va()300 if (xlat_regime == EL1_EL0_REGIME) { in setup_mmu_cfg()
41 if (ctx->xlat_regime == EL1_EL0_REGIME) { in is_mpu_enabled_ctx()
47 tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME; in init_xlat_tables()
325 (ctx->xlat_regime == EL1_EL0_REGIME)); in init_xlat_tables_ctx()
33 EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME,
122 EL1_EL0_REGIME); in spm_sp_setup()
154 #define EL1_EL0_REGIME 1 macro
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