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Searched refs:ENABLE (Results 1 – 3 of 3) sorted by relevance

/trusted-firmware-a/plat/rockchip/rk3399/drivers/m0/src/
A Dstopwatch.c15 #define ENABLE (1 << 0) macro
40 mmio_write_32(SYST_CST, ENABLE | TICKINT | CLKSOURCE); in stopwatch_set_usecs()
49 if (mmio_read_32(SYST_CST) & ENABLE) in stopwatch_init_usecs_expire()
60 if ((val & COUNTFLAG) || !(val & ENABLE)) { in stopwatch_expired()
72 mmio_clrbits_32(SYST_CST, ENABLE); in stopwatch_reset()
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/
A Dplat_memctrl.c42 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
65 mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
67 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
70 mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
74 mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
76 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
87 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
104 mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
/trusted-firmware-a/docs/build/latex/
A Dtrustedfirmware-a.tex4141 used on systems that have SPD=spmd/SPM\_MM or ENABLE\_RME, and attempting to
4165 default and controlled with ENABLE\_SVE\_FOR\_SWD.
4170 1. The default is 1 but is automatically disabled when ENABLE\_SME\_FOR\_NS=1
4178 requires ENABLE\_SVE\_FOR\_NS to be enabled. The default is 0 and it is
11749 using the \sphinxcode{\sphinxupquote{ENABLE\_ASSERTIONS}} build flag.
24202 To enable RME, you need to set the ENABLE\_RME build flag when building
24220 ENABLE\_RME build option is currently experimental.
43212 the \sphinxcode{\sphinxupquote{ENABLE\_RUNTIME\_INSTRUMENTATION}} option:
58690 socionext: uniphier: Turn on ENABLE\_PIE
58809 BL31: Discard .dynsym .dynstr .hash sections to make ENABLE\_PIE work
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