1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CCI_H 8 #define CCI_H 9 10 #include <lib/utils_def.h> 11 12 /* Slave interface offsets from PERIPHBASE */ 13 #define SLAVE_IFACE6_OFFSET UL(0x7000) 14 #define SLAVE_IFACE5_OFFSET UL(0x6000) 15 #define SLAVE_IFACE4_OFFSET UL(0x5000) 16 #define SLAVE_IFACE3_OFFSET UL(0x4000) 17 #define SLAVE_IFACE2_OFFSET UL(0x3000) 18 #define SLAVE_IFACE1_OFFSET UL(0x2000) 19 #define SLAVE_IFACE0_OFFSET UL(0x1000) 20 #define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \ 21 (UL(0x1000) * (index))) 22 23 /* Slave interface event and count register offsets from PERIPHBASE */ 24 #define EVENT_SELECT7_OFFSET UL(0x80000) 25 #define EVENT_SELECT6_OFFSET UL(0x70000) 26 #define EVENT_SELECT5_OFFSET UL(0x60000) 27 #define EVENT_SELECT4_OFFSET UL(0x50000) 28 #define EVENT_SELECT3_OFFSET UL(0x40000) 29 #define EVENT_SELECT2_OFFSET UL(0x30000) 30 #define EVENT_SELECT1_OFFSET UL(0x20000) 31 #define EVENT_SELECT0_OFFSET UL(0x10000) 32 #define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \ 33 (UL(0x10000) * (index))) 34 35 /* Control and ID register offsets */ 36 #define CTRL_OVERRIDE_REG U(0x0) 37 #define SECURE_ACCESS_REG U(0x8) 38 #define STATUS_REG U(0xc) 39 #define IMPRECISE_ERR_REG U(0x10) 40 #define PERFMON_CTRL_REG U(0x100) 41 #define IFACE_MON_CTRL_REG U(0x104) 42 43 /* Component and peripheral ID registers */ 44 #define PERIPHERAL_ID0 U(0xFE0) 45 #define PERIPHERAL_ID1 U(0xFE4) 46 #define PERIPHERAL_ID2 U(0xFE8) 47 #define PERIPHERAL_ID3 U(0xFEC) 48 #define PERIPHERAL_ID4 U(0xFD0) 49 #define PERIPHERAL_ID5 U(0xFD4) 50 #define PERIPHERAL_ID6 U(0xFD8) 51 #define PERIPHERAL_ID7 U(0xFDC) 52 53 #define COMPONENT_ID0 U(0xFF0) 54 #define COMPONENT_ID1 U(0xFF4) 55 #define COMPONENT_ID2 U(0xFF8) 56 #define COMPONENT_ID3 U(0xFFC) 57 #define COMPONENT_ID4 U(0x1000) 58 #define COMPONENT_ID5 U(0x1004) 59 #define COMPONENT_ID6 U(0x1008) 60 #define COMPONENT_ID7 U(0x100C) 61 62 /* Slave interface register offsets */ 63 #define SNOOP_CTRL_REG U(0x0) 64 #define SH_OVERRIDE_REG U(0x4) 65 #define READ_CHNL_QOS_VAL_OVERRIDE_REG U(0x100) 66 #define WRITE_CHNL_QOS_VAL_OVERRIDE_REG U(0x104) 67 #define MAX_OT_REG U(0x110) 68 69 /* Snoop Control register bit definitions */ 70 #define DVM_EN_BIT BIT_32(1) 71 #define SNOOP_EN_BIT BIT_32(0) 72 #define SUPPORT_SNOOPS BIT_32(30) 73 #define SUPPORT_DVM BIT_32(31) 74 75 /* Status register bit definitions */ 76 #define CHANGE_PENDING_BIT BIT_32(0) 77 78 /* Event and count register offsets */ 79 #define EVENT_SELECT_REG U(0x0) 80 #define EVENT_COUNT_REG U(0x4) 81 #define COUNT_CNTRL_REG U(0x8) 82 #define COUNT_OVERFLOW_REG U(0xC) 83 84 /* Slave interface monitor registers */ 85 #define INT_MON_REG_SI0 U(0x90000) 86 #define INT_MON_REG_SI1 U(0x90004) 87 #define INT_MON_REG_SI2 U(0x90008) 88 #define INT_MON_REG_SI3 U(0x9000C) 89 #define INT_MON_REG_SI4 U(0x90010) 90 #define INT_MON_REG_SI5 U(0x90014) 91 #define INT_MON_REG_SI6 U(0x90018) 92 93 /* Master interface monitor registers */ 94 #define INT_MON_REG_MI0 U(0x90100) 95 #define INT_MON_REG_MI1 U(0x90104) 96 #define INT_MON_REG_MI2 U(0x90108) 97 #define INT_MON_REG_MI3 U(0x9010c) 98 #define INT_MON_REG_MI4 U(0x90110) 99 #define INT_MON_REG_MI5 U(0x90114) 100 101 #define SLAVE_IF_UNUSED -1 102 103 #ifndef __ASSEMBLER__ 104 105 #include <stdint.h> 106 107 /* Function declarations */ 108 109 /* 110 * The ARM CCI driver needs the following: 111 * 1. Base address of the CCI product 112 * 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave 113 * interfaces. 114 * 3. Size of the array. 115 * 116 * SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists 117 * for that interface. 118 */ 119 void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters); 120 121 void cci_enable_snoop_dvm_reqs(unsigned int master_id); 122 void cci_disable_snoop_dvm_reqs(unsigned int master_id); 123 124 #endif /* __ASSEMBLER__ */ 125 #endif /* CCI_H */ 126